Physical Design Lead
PH-011 | Founding Technical Staff | Boston, MA | Onsite | $140K – $200K base + equity
About Prahelika
Prahelika is building the domestic integration layer: 3D systems in which III-V semiconductors, state-of-the-art silicon, and novel interposers are stacked into one device, each doing what it does best. We co-design the signal path, the power tier, the thermal path, and the manufacturing process, so dies from any foundry become a system that silicon alone cannot deliver. Our first 3D systems serve defense radar and low-Earth-orbit satellite communications; the same platform extends to power electronics, data-center compute, and photonics. Backed by top-tier investors and built by engineers who demonstrated every tier of the stack as measured hardware before the company existed, Prahelika owns the layer between the transistor and the machine. Ultimate electronics through integration.
The role
Whoever owns a design here sees it through fabrication, packaging, measurement, shipping, and the next revision. A 3D system is not one layout; it is several, in different foundry design kits, plus the interposer and redistribution layers that connect them, and every one of them has to be clean, aligned to the others, and out the door on the same day. A tape-out slips by the month when the designers are also the layout team.
You will make sure it does not. As our physical design lead, you own physical design across every die and package layer of our first products: front-end and back-end layout in each foundry process, silicon and glass interposer layout, the tech files and rule decks for each, DRC/LVS and parasitic extraction, die-to-interposer alignment and pad rules, and the final GDS. In industry these are usually three positions; here they are one, and the substrate and package design that sits alongside them is a separate hire you will help make. You sit between the RFIC/MMIC, analog, EM, and integration engineers, and the rules you write become the manufacturing half of the design kit.
Required qualifications
B.S. or M.S. in Electrical Engineering with 6+ years of analog, RF, or mixed-signal physical design on chips that taped out and shipped, spanning front-end (device-level) and back-end (BEOL) layout. Equivalent practical experience may substitute for the degree requirement.
Fluency in Cadence Virtuoso Layout and Innovus and the sign-off flow (Calibre or PVS DRC/LVS, parasitic extraction) in at least two foundry PDKs, including one compound-semiconductor or one RF-SOI/SiGe process.
Experience building or maintaining tech files, layer maps, and rule decks, setting up a new PDK from foundry deliverables, and familiarity with the design-database sign-off flows of the major foundries.
Hands-on experience in at least two of the following:
Package, interposer, or redistribution-layer layout (Cadence Allegro/APD, Siemens Xpedition, or equivalent) and die-to-package co-layout.
Silicon-interposer or glass-interposer physical design, including TSV/TGV rules, RDL routing, and interposer-level sign-off.
Multi-die or chiplet assembly layout: pad maps, bump/pillar rules, alignment and keep-out, and assembly design kits.
Layout automation: SKILL, Python, or PCell development that removed manual steps from a tape-out.
This role involves work that may be subject to U.S. export-control laws. Prahelika assesses access requirements for the specific work and, where needed, evaluates available government authorization options before granting access to controlled technology. Program assignments are subject to applicable legal requirements.
Preferred qualifications
Wafer-level or panel-level packaging layout, or glass and other non-organic substrates.
Experience with tape-out logistics across multiple foundries and shuttle schedules.
Responsibilities
Own physical design for every die and package layer of our first products, from floorplan through final GDS, in each foundry PDK and our own interposer rules.
Set up and maintain the tech files, rule decks, and sign-off flows for every process we use, and be the person who knows why a rule exists.
Run DRC, LVS, and extraction to closure on schedule, and drive the tape-out checklist across every die and layer at once.
Work with the EM and integration engineers to write the die-to-interposer and assembly rules, and with the ML engineer to automate what you find yourself doing twice.
Establish the layout rules and assembly design kit that become the manufacturing half of Prahelika's design kit.
How we work
Engineers here work across the stack. Siloed circuit, device, and package engineers do not thrive at Prahelika; you will be expected to understand the neighboring disciplines well enough to argue with them.
AI is a cornerstone of how we engineer. You will build your own workflows with tools such as Claude, ChatGPT, or Codex, compatible with Prahelika's AI ecosystem, with physically grounded checks on what they produce.
No one is asked to cut a corner they would be ashamed to defend. If a deadline can only be met by skipping a reliability test, the deadline moves, and the engineer who refuses to sign off on something unsound is protected, not punished.
Credit and authorship follow contribution, not seniority. If your name belongs on the work, it is there.
Excellence of mind and body is a working condition, not a reward for finishing. Tired decisions end up in hardware; we expect you to sleep, train, and step away, and we do not mistake hours logged for work delivered.
Compensation and benefits
$140K – $200K base salary plus founding-team equity. Final compensation depends on experience and skills.
Full medical, dental, and vision coverage with HSA; 401(k) with 4% company match; daily meals.
How to apply
Apply using the form for this role. If available, please include a brief description of one project that best represents your work on this kind of problem; we read that more closely than a cover letter.
Prahelika is an equal opportunity employer. We hire on demonstrated ability, without regard to any protected characteristic.