RD-數位後端設計工程師 ASIC Physical Design / APR Engineer (Back-End)

【Key Responsibilities / 工作內容】
1. Physical Implementation (Netlist-to-GDSII)：Lead full floorplanning, placement, Clock Tree Synthesis (CTS), and routing (PNR) for complex block and top-level designs.
2. Advanced Node Optimization：Solve design issues on advanced node processes , addressing multi-patterning, LDE, and crosstalk noise.
3. Sign-off & Closure：Execute timing closure (STA), power integrity analysis (Static/Dynamic IR-Drop, EM), and Physical Verification (DRC, LVS, ERC).
4. Low Power & DFT Integration：Implement multi-voltage domains, power gating (UPF/CPF), and integrate scan chains / MBIST into physical flows.
5. Flow Development：Develop and maintain automated APR and sign-off scripts to improve execution efficiency and PPA (Power, Performance, Area).
【Requirements & Qualifications / 條件要求】

• Education：MS/BS in Electrical Engineering, Computer Science, or related fields.
• Technical Skills：

1. Expert in APR EDA tools: Synopsys ICC2 / Fusion Compiler or Cadence Innovus.
2. Proficient in sign-off tools: PrimeTime / Tempus (STA), Voltus / RedHawk (IR-drop), and Calibre (DRC/LVS).
3. Strong mastery of scripting languages (Tcl, Python, Shell).
4. Experience with full Tape-out flow is a big plus.