Senior ASIC Backend Layout Engineer - P&R & Timing Lead
Summary
Senior ASIC backend engineer leading place-and-route and timing closure for semiconductor designs using Cadence Innovus or Synopsys ICC2.
Dormont Manufacturing Co is seeking an experienced Senior Digital Backend Layout Engineer to join our semiconductor engineering team. In this role, you'll manage backend design flows, optimize layouts for performance and area, and ensure DRC/LVS compliance.
With 5+ years in digital backend design, proficiency in tools like Cadence Innovus and Synopsys ICC2 is required. This is a full-time position based at our Saratoga office, offering competitive salaries and opportunities for professional growth.