Y Combinator Senior ASIC RTL Design Engineer
Summary
Designs and optimizes ASIC RTL (Register Transfer Level) logic for hardware chips, ensuring functionality, performance, and manufacturability in a full-time onsite role at an engineering services company.
3 weeks ago
ASIC RTL Design Engineer
APACFull-time
India
Design and implement synthesizable RTL for complex ASICs using Verilog/SystemVerilog, optimizing for power, performance, and area while collaborating with verification and physical design teams.
systemverilog verilog
3 000 000 – 5 000 000 INR 3 weeks ago
ASIC RTL Design Engineer
APACFull-time
India
Designs and verifies RTL for AI accelerators and ASICs, optimizing hardware for machine-learning workloads.
systemverilog verilog
3 weeks ago
RTL Design
APACFull-time
India
Designs and verifies RTL (Register Transfer Level) logic for AI hardware accelerators using Verilog/VHDL and industry-standard EDA tools.
automation fpga perl prototyping python +3 skills
3 weeks ago
ASIC RTL Design Engineer
APACFull-time
India
Designs and implements RTL for AI accelerators and ASICs, optimizing for performance and power efficiency.
automation perl python systemverilog tcl +1 skills
4 weeks ago
Senior RTL Design Engineer, TPU
North AmericaSenior
United States
Design and verify custom silicon for Google’s TPU AI accelerators, focusing on management/control subsystems and SoC integration.
ai cloud gcp machine-learning networking +6 skills
163 000 – 236 000 $