Senior DDR Design Verification Engineer, Google Cloud
Posted
Summary
Senior engineer verifying digital designs for custom silicon (DDR PHY/Controller/SoC) within Google Cloud. Day-to-day involves building verification environments, constrained-random testing, and closing coverage using SystemVerilog, UVM, and SVA to ensure hardware reliability for AI and infrastructure scale.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing. You will verify digital designs, collaborate closely with colleagues on projects, and perform direct validation. You will construct testbenches that exercise hardware through corner-cases and expose bugs. You will manage the full life-cycle from planning and execution to closing coverage.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
- Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
- Identify and write all types of coverage measures for corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 8 years of experience with creating and using verification components and environments in standard verification methodology.
- Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, or a related field.
- Experience with verification techniques, and the full verification life cycle.
- Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
- Experience with performance verification of ASICs and ASIC components.
- Experience in DDR PHY/Controller verification activities.
- Experience in DDR SoC integration and verification.