Senior Design Verification Engineer
Summary
Senior design verification engineer on Google's custom silicon team, verifying micro-display chips for direct-to-consumer AR/VR products: building SystemVerilog/UVM testbenches, C/C++ DPI reference models, coverage-driven verification, and running emulation on platforms like Palladium, Zebu, and Veloce.
- Define comprehensive verification strategies, test architectures, and detailed test plans covering full chip, subsystem, and block levels.
- Architect scalable SystemVerilog and Universal Verification Methodology (UVM) verification environments with constrained-random stimulus generation, protocol checkers, and automated scoreboards.
- Establish bit-accurate reference models using C/C++ integrated via Direct Programming Interface (DPI)-C to verify complex pixel-processing algorithms and video pipelines dynamically.
- Formulate metric-motivated verification methodologies, tracking functional coverage, code coverage (e.g., line, branch, toggle, expression), and assertion density.
- Verify high-speed protocol interfaces and link layers against industry standards, including packetization, link training, error management, and recovery mechanisms.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
- Experience with ultra-low latency, high-density micro-display technologies.
- Experience transitioning UVM testbenches to hardware emulation platforms.
- Experience with scripting languages such as Python or Perl or Makefile.
Preferred qualifications:
- Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
- Experience with tools such as MicroLED, Micro-Organic Light Emitting Diode (OLED) for Augmented Reality/Virtual Reality/Extended Reality. (AR/VR XR) systems.
- Expertise with Palladium, Zebu and Veloce.