Senior Design Verification Engineer(台北)

1.Develop verification strategies, test plans, and verification methodologies based on architecture and design specifications.
2.Build and maintain UVM-based verification environments for IP, subsystem, and SoC-level verification.
3.Develop reusable UVM verification components, including agents, drivers, monitors, sequencers, scoreboards, reference models, checkers, and coverage models.
4.Create directed, constrained-random, and stress testcases to verify functionality, protocol compliance, and corner-case scenarios.
5.Develop functional coverage, assertions, and coverage-driven verification methodologies to ensure verification completeness.
6.Perform RTL and testbench debugging, root-cause analysis, and collaborate closely with design engineers to resolve design issues.
7.Review architecture and design specifications to identify verification gaps and improve overall design quality.
8.Integrate and customize commercial VIPs or internal BFMs for standard protocols such as PCIe, CXL, UCIe, DDR, AXI, AHB, and APB.
9.Execute regression testing, analyze failures, track bugs, and drive issue resolution through verification sign-off.
10Support gate-level simulation, CDC/reset verification, low-power verification, formal verification, emulation, FPGA prototyping, and post-silicon validation when required.
11.Prepare and maintain verification documentation, including verification plans, coverage reports, verification metrics, and verification closure reports.
12.Collaborate closely with architecture, RTL design, firmware, validation, and system teams throughout the entire product development cycle.

1.根據產品架構與設計規格制定驗證策略、測試計畫及驗證方法。
建立與維護以 UVM 為基礎的驗證環境，執行 IP、Subsystem 及 SoC 層級驗證。
2.開發可重複使用的 UVM 驗證元件，包括 Agent、Driver、Monitor、Sequencer、Scoreboard、Reference Model、Checker 及 Coverage Model。
3.撰寫 Directed Test、Constrained-Random Test 與 Stress Test，驗證功能、協定相容性及各種 Corner Case。
4.建立 Functional Coverage、Assertion 與 Coverage-Driven Verification 流程，確保驗證完整性。
5.進行 RTL 與 Testbench 除錯、Root Cause Analysis，並與設計工程師合作解決問題。
6.參與架構及設計規格審查，找出驗證缺口並提升整體設計品質。
7.整合並客製化商用 VIP 或內部 BFM，支援 PCIe、CXL、UCIe、DDR、AXI、AHB、APB 等標準介面驗證。
8.執行 Regression 測試、分析失敗案例、追蹤 Bug，並完成 Verification Sign-off。
9.視專案需求支援 Gate-Level Simulation、CDC／Reset 驗證、Low-Power Verification、Formal Verification、Emulation、FPGA Prototype 及 Post-Silicon Validation。
10撰寫並維護驗證相關文件，包括 Verification Plan、Coverage Report、Verification Metrics 及 Verification Closure Report。
11.與 Architecture、RTL Design、Firmware、Validation 及 System Team 密切合作，共同完成產品開發。