Senior Design Verification Engineer
Posted Updated
Summary
Develops and executes verification strategies and environments for complex SoC hardware — building UVM/SystemVerilog testbenches, assertions, formal and emulation flows, verifying compute, memory, and interconnect blocks, and supporting emulation, FPGA prototyping, pre-silicon bring-up, and post-silicon debug.
You will develop verification strategies and environments for complex SoC hardware. You will validate system behavior, performance, reliability, safety, low-power behavior, clocking, and reset behavior, while supporting emulation, FPGA prototyping, pre-silicon bring-up, and post-silicon debug.
Responsibilities
- Develop and execute verification strategies for SoC components
- Build verification environments using SystemVerilog, UVM, C/C++, assertions, formal verification, and emulation
- Define verification plans, coverage goals, and correctness criteria
- Verify compute engines, memory subsystems, interconnects, processors, DMA engines, and SoC infrastructure
- Perform hardware/software co-verification
- Verify performance, latency, bandwidth, QoS, and real-time behavior
- Develop assertions, checkers, scoreboards, and automated verification infrastructure
- Participate in emulation, FPGA prototyping, and pre-silicon software bring-up
- Investigate bugs and perform root-cause analysis across hardware and software
- Perform post-silicon debug and root-cause analysis
Requirements
- 10+ years verifying complex digital systems
- Computer architecture
- Microarchitecture
- SoC architecture
- Digital design
- Low-power verification
- Clock-domain crossing verification
- Clocking verification
- Reset verification
- SystemVerilog
- UVM
- C/C++
- Assertions
- Coverage-driven verification
- Formal verification
- Emulation or FPGA prototyping
- System-level debugging
Benefits
- Competitive equity compensation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements