Senior Digital Design Engineer

1. 4/5/6G modem Hardware platform IP and Subsys digital design and PPA optimization
2. Define hardware architecture of a digital IP/system: Include Clock, Bus (AXI/APB/NOC/…), Async design, high speed IF, new IP for sub-sys design topic
3. Subsys integration from RTL to gate level including timing closure and testability
4. Design methodology and integration flow improvement

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