Senior Digital Design Engineer

1. 4/5/6G modem Hardware platform IP and Subsys digital design and PPA optimization
2. Define hardware architecture of a digital IP/system: Include Clock, Bus (AXI/APB/NOC/…), Async design, high speed IF, new IP for sub-sys design topic
3. Subsys integration from RTL to gate level including timing closure and testability
4. Design methodology and integration flow improvement

#LI-LL1

1. Have some experiences in digital IP/subsys design and flow ( Architecture design, RTL Coding, design Integration, verification, PPA optimization)
2. Have some experiences in front-end or back-end implementation flow and related EDA tools
3. Better to have experience in clock tree structure and power analysis flow
4. Better to have experience in SoC platform architecture including MCU, Bus, Cache, clock , reset and debug system
5. Better to have knowledge about 4/5G Modem User Plane System, IP Layer Function