Senior Engineer CAD Pre Silicon Front End

You will own front-end automation from RTL entry through DFT and implementation handoff. You will maintain design, verification, emulation, and FPGA prototyping flows; build AI-assisted tools; manage tool availability; and improve engineering productivity.

Responsibilities

• Own RTL build, lint, CDC, and formal-check flows
• Own register generation and generator-driven interface and integration flows
• Own DV testbench, regression, and coverage flows
• Own emulation and FPGA prototyping build and bring-up
• Build and deploy AI-assisted tooling for design and verification workflows
• Manage tool versions, bugs, upgrades, and maintenance requests
• Measure and improve design and verification productivity
• Partner on DFT and physical-design handoff readiness

Requirements

• Design verification
• CAD engineering
• SystemVerilog
• RTL
• Simulation
• Regression testing
• Testbench
• Coverage analysis
• Python
• EDA
• Linux administration
• Distributed computing
• LSF
• Slurm
• Database
• Grafana
• Issue management

Benefits

• Equity compensation
• Medical coverage
• Dental coverage
• Vision coverage
• Paid time off
• Flexible work arrangements