Senior RFIC/MMIC Design Engineer

PH-001 | Founding Technical Staff | Boston, MA | Onsite | $150K – $220K base + equity

About Prahelika

Prahelika is building the domestic integration layer: 3D systems in which III-V semiconductors, state-of-the-art silicon, and novel interposers are stacked into one device, each doing what it does best. We co-design the signal path, the power tier, the thermal path, and the manufacturing process, so dies from any foundry become a system that silicon alone cannot deliver. Our first 3D systems serve defense radar and low-Earth-orbit satellite communications; the same platform extends to power electronics, data-center compute, and photonics. Backed by top-tier investors and built by engineers who demonstrated every tier of the stack as measured hardware before the company existed, Prahelika owns the layer between the transistor and the machine. Ultimate electronics through integration.

The role

Whoever owns a design here sees it through fabrication, packaging, measurement, shipping, and the next revision. On a compound-semiconductor wafer, the transistor is the least of the real estate: most of the area, most of the loss, and most of the cost is the network around it. Our 3D systems cut the transistor out of the wafer and build that network in the package, on materials chosen for the job, which means the circuit designer and the package designer are the same person.

You will be that person for our first products. As our first RFIC/MMIC design engineer, you own the front-end circuits from device selection through matching, layout, tape-out, bench, and revision, across III-V and silicon dies that arrive from different foundries and meet in one package. The design flow you establish with the electromagnetics and thermal engineers becomes the kit every later RF designer at Prahelika uses.

Required qualifications

• M.S. with 5+ years or Ph.D. with 2+ years designing RF or millimeter-wave integrated circuits that were taped out, measured, and delivered, in industry, a national lab, or a postdoc. Equivalent practical experience may substitute for the degree requirement.

• At least one product-grade GaN, GaAs, or InP MMIC and one RF or mmWave circuit in a silicon process (CMOS, SiGe, or RF-SOI) with your name on the tape-out.

• Fluency in Keysight ADS or Cadence Virtuoso/Spectre RF, plus a 3D EM solver (HFSS, EMX, or equivalent) for passives and package co-simulation.

• Hands-on experience in at least two of the following:

  • Power amplifier design: Doherty, load-modulated, or switched-mode topologies, with measured PAE and linearity under modulated signals.

  • Load-pull, large-signal, and nonlinear device model extraction and validation on your own bench data.

  • Phased-array or beamformer front-end design: T/R switches, LNAs, phase shifters, or bias and protection circuits.

  • Packaged or heterogeneously integrated RF design where the interposer, RDL, or bond interface was inside your matching network.

• This role involves work that may be subject to U.S. export-control laws. Prahelika assesses access requirements for the specific work and, where needed, evaluates available government authorization options before granting access to controlled technology. Program assignments are subject to applicable legal requirements.

Preferred qualifications

• Multi-chip or chiplet-based RF front ends across more than one foundry process.

• Experience taking an RF module through a prime-contractor or space qualification flow.

Responsibilities

• Own the RF circuit design for our first products, from device selection and topology through matching, layout, and tape-out, on dies from multiple foundries.

• Co-design the signal path with the electromagnetics engineer so that package interconnects, transitions, and embedded passives are part of the circuit, not parasitics added afterward.

• Set the load-line, bias, and linearity budgets that the thermal and analog engineers design around, and hold the design to them on the bench.

• Characterize your own hardware: small-signal, load-pull, large-signal, and modulated measurements, with results fed into the next revision and into our device and package models.

• Establish the RF design flow, model library, and sign-off checks that become part of Prahelika's design kit, and mentor the RF designers who follow.

How we work

• Engineers here work across the stack. Siloed circuit, device, and package engineers do not thrive at Prahelika; you will be expected to understand the neighboring disciplines well enough to argue with them.

• AI is a cornerstone of how we engineer. You will build your own workflows with tools such as Claude, ChatGPT, or Codex, compatible with Prahelika's AI ecosystem, with physically grounded checks on what they produce.

• No one is asked to cut a corner they would be ashamed to defend. If a deadline can only be met by skipping a reliability test, the deadline moves, and the engineer who refuses to sign off on something unsound is protected, not punished.

• Credit and authorship follow contribution, not seniority. If your name belongs on the work, it is there.

• Excellence of mind and body is a working condition, not a reward for finishing. Tired decisions end up in hardware; we expect you to sleep, train, and step away, and we do not mistake hours logged for work delivered.

Compensation and benefits

• $150K – $220K base salary plus founding-team equity. Final compensation depends on experience and skills.

• Full medical, dental, and vision coverage with HSA; 401(k) with 4% company match; daily meals.

How to apply

Apply using the form for this role. If available, please include a brief description of one project that best represents your work on this kind of problem; we read that more closely than a cover letter.

Prahelika is an equal opportunity employer. We hire on demonstrated ability, without regard to any protected characteristic.