Senior RTL Design Engineer - Cache Subsystem

The Role:

As a Cache Subsystem Microarchitect and RTL design engineer at SiFive you will be part of a team of engineers who are passionate about designing industry-leading CPU cores and cache subsystems, based on the revolutionary open-source RISC-V architecture. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.

Responsibilities

• You will architect, design and implement new high performance cache subsystems in SiFive's RISC-V CPU core generators and enhance features and performance in existing ones.
• Work on the microarchitecture development and specification; ensuring that knowledge is shared via great documentation and participation in a collaborative design culture.
• Perform initial sandbox verification and work closely with the verification team to create and execute detailed verification test plans.
• Work with the physical implementation team to implement and optimize physical design to meet frequency, area, power goals.
• Collaborate with the performance modelling team for performance exploration and optimization to meet performance goals.