Senior Staff Design Verification Engineer
Posted Updated 4
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Summary
Senior design verification engineer working on Cerebras' AI chips: develops verification strategies, reusable SystemVerilog/UVM testbenches and coverage plans, manages regressions, and debugs failures across simulation, emulation, and silicon bring-up while improving verification infrastructure.
You will develop verification strategies, tests, coverage plans, and reusable verification environments. You will manage regressions, debug failures across simulation, emulation, and silicon bring-up, and improve verification methodologies and infrastructure with cross-functional engineering partners.
Responsibilities
- Develop verification strategies, tests, and coverage plans
- Create reusable verification environments with stimulus, checkers, assertions, and coverage
- Implement tests and manage regressions
- Gather coverage and debug test failures
- Analyze issues across simulation, emulation, and silicon bring-up
- Improve verification infrastructure, flows, and methodologies
Requirements
- 15+ years of design verification experience
- SystemVerilog testbench, DPI, and UVM knowledge
- Programming and object-oriented design skills
- Scalable and portable testbench development
- Verification simulators, waveform viewers, automation, coverage collection, and gate-level simulation
- Python or Perl scripting
Benefits
- Bonus
- Equity