設計驗證工程師 (Design Verification Engineer)

✅ About the job
Responsible for SoC-level/IP-level environment verification to ensure the circuit architecture and functional behavior align with design specifications.

✅ Key Responsibilities
1. Verify designs with system-verilog and UVM environment.
2. Support debug design issues and co-work with design engineers.
3. Collect coverage and identify missing coverage points.
4. Familiar with Tcl and Python for regression scripts.
5. Familiar with AMBA specifications and protocols.
6. Familiar with Synopsys AMBA VIP.

✅ Qualifications
1. VCS / VERDI
2. UVM / SV / TCL / PYTHON
3. AMBA

✅ Nice to have
1. Familiar with PCIE specifications and protocols.
2. Familiar with LPDDR specifications and protocols.