數位IC設計工程師0300

【About the Team】
We are leading the industry in UFS 4.0 and pioneering the development of UFS 5.0. We are looking for an engineer to help us build the world's most advanced UFS controllers, pushing the limits of storage performance and power efficiency.

【Key Responsibilities】
1. High-Speed Interface & System Integration Lead the integration of UFS, UniPro, and NAND Flash IPs with CPU clusters and system bus fabrics. You will optimize the interaction between these high-speed peripherals to ensure optimal throughput, latency, and power efficiency.
2. SoC Infrastructure & RTL Design Design and implement core SoC infrastructure, including clock/reset schemes and UPF power flows. You will also be responsible for ATE planning (Scan/MBIST/Analog Macro) to ensure high-quality silicon realization.
3. Design Validation & Sign-off Execution Drive the complete front-end delivery pipeline. This includes developing UVM verification environments at the block and SoC levels, and performing precise sign-off using NCVerilog, Verdi, Lint, CDC, and Formal Verification. You will leverage FPGA prototyping and Emulation platforms to accelerate bug discovery and guarantee a flawless tape-out.