SoC Design Verification Engineer

You will plan and execute system-level verification for assigned SoC areas. You will build simulation environments, verify boot, security, clock, reset, power, IO, and memory subsystems, run CDC and RDC analysis, assess system performance, and support coverage closure, sign-off, and tape-out readiness.

Responsibilities

• Drive verification planning and execution for assigned SoC areas
• Build and maintain SoC-level simulation environments and flows
• Verify boot flows, root of trust, security state transitions, and firmware handoff
• Verify clock and reset topology, power domains, and low-power behavior
• Verify IO and memory subsystem integration including PCIe and LPDDR
• Run SoC-level CDC and RDC analysis and close findings with design teams
• Verify system-level latency, bandwidth, and QoS under representative workloads
• Support SoC sign-off criteria, coverage closure, and tape-out readiness

Requirements

• 10 or more years in design verification, including significant SoC-level experience
• Experience leading or participating in multiple SoC verification projects, including sign-off and tape-out
• Experience with SystemVerilog, UVM, C, C++, and coverage-driven verification at system level
• Experience managing simulation flows on CPU-based SoCs such as ARM or RISC-V
• Knowledge of IO and memory subsystem IP such as PCIe and LPDDR5 or LPDDR6
• Experience verifying boot sequences and root of trust
• Experience verifying clock and reset topology at system level, with hands-on use of CDC and RDC tools
• Experience with low-power verification tools and UPF-based flows

Benefits

• Equity compensation
• Medical coverage
• Dental coverage
• Vision coverage
• Paid time off
• Flexible work arrangements