SoC Physical Design Engineer_ChuPei

1. Work on 2~4nm design implementation, methodology, and sign-off
2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification
3. Manage schedule, resolve design and flow issues, drive methodologies and execution

Requirements

1. MS +2yrs in EE/CS
2. SYN/APR/Signoff hands-on and tapeout experience in deep submicron technology
3. Tcl/Perl/script/C/C++ programming skill
4. Strong communication skill
Education: Master's Degree