Sr Manager Package SIPI, Annapurna Labs
Posted Updated
Description
About the Role
We are looking for a Senior Manager of Package Signal & Power Integrity to lead a small team of engineers delivering SI/PI solutions for next-generation 2.5D/3D chiplet-based products. This is a player-coach role: you will set the technical direction for package-level SI/PI across advanced packaging platforms (CoWoS, EMIB, 3D die stacking) while staying hands-on with modeling, simulation, and post-silicon correlation.
You will own the SI/PI strategy from early architecture through high-volume production, partnering with silicon design, physical design, system architecture, and possible with OSAT/substrate vendors to ensure robust signaling and power delivery across die-to-die, memory, and high-speed SerDes interfaces.
What You Will Do
• Lead and develop a team of SI/PI engineers, setting priorities, driving career growth, and building world-class packaging expertise.
• Define and execute SI/PI design methodology for 2.5D/3D IC packages—including silicon interposer, RDL, TSV, and bridge-based architectures.
• Drive chip-package-system co-design by performing end-to-end SI/PI analysis and optimization for HBM (HBM3/HBM3E+), PCIe Gen5/Gen6/Gen7, UCIe die-to-die interconnects and high-speed SerDes (112G+/224G PAM4).
• Own PDN design and sign-off across die, interposer, package substrate, and PCB, including AC/DC/transient droop analysis and decoupling strategy.
• Develop and validate channel models (S-parameter, IBIS-AMI) and perform BER/eye-diagram analysis for multi-lane high-speed links.
• Establish SI/PI design guidelines, sign-off criteria, and automation flows; drive continuous improvement in accuracy and productivity.
• Partner with ASIC architects, PHY/IP teams, package layout, thermal/mechanical, PCB, and system design teams to close electrical specifications.
• Collaborate with other internal partners and external partners (possible like foundry, OSAT, and substrate suppliers etc.) on technology assessment, DFM trade-offs, and new package platform enablement.
• Lead post-silicon validation and model-to-hardware correlation using VNA, TDR, oscilloscope, and spectrum analyzer measurements.
Required Qualifications
• MS or PhD in Electrical Engineering, with emphasis in electromagnetics, signal integrity, power integrity, or microelectronics.
• 12+ years of progressive SI/PI engineering experience in semiconductor packaging (IC package, interposer, or substrate design).
• 3+ years of direct people-management experience leading SI/PI or packaging engineering teams.
• Demonstrated expertise in 2.5D/3D advanced packaging technologies (CoWoS-S/L/R, EMIB, Foveros, 3D die stacking, TSV, RDL, flip-chip BGA).
• Hands-on experience with SI/PI analysis for high-speed SerDes interfaces at 56G NRZ / 112G+ PAM4 data rates.
• Strong background in HBM3/4 SI/PI design and timing budget methodology (HBM3/HBM3E/HBM4 or newer).
• Experience with PCIe Gen5/Gen6 channel design, compliance, and sign-off at the package and system level.
• Working knowledge of UCIe or comparable die-to-die interconnect standards for chiplet architectures.
• Proficiency in industry EDA/simulation tools: Ansys HFSS/SIwave/Q3D, Cadence Sigrity (PowerSI, SystemSI), Keysight ADS, HSPICE/Spectre.
• Strong scripting skills (Python, MATLAB, Tcl) for simulation automation and data analysis.
• Proven ability to drive cross-functional alignment across silicon, package, board, and system teams in a fast-paced product environment.
Preferred Qualifications
• Experience with PCIe Gen7, 200G/400G Ethernet SerDes, or NVLink-class ultra-high-speed interconnects.
• Expertise in UCIe advanced (UCIe 2.0) protocol-level SI/PI considerations and latency-sensitive chiplet integration.
• Familiarity with next-generation HBM standards (HBM4e) and associated PHY/package co-design challenges.
• Track record of new product introduction (NPI) from concept through high-volume manufacturing.
• Experience with on-die EMIR/DVD analysis and chip-package PDN co-simulation workflows.
• Exposure to EMI/EMC analysis and mitigation at the package and system level.
• Knowledge of thermal-aware SI/PI design—understanding package warpage, material Dk/Df drift, and reliability impacts on signal performance.
• Experience evaluating emerging packaging platforms (glass substrate, hybrid bonding, fan-out panel-level packaging).
• Active participation in industry standards bodies (IEEE, UCIe Consortium, JEDEC, OIF).
We are looking for a Senior Manager of Package Signal & Power Integrity to lead a small team of engineers delivering SI/PI solutions for next-generation 2.5D/3D chiplet-based products. This is a player-coach role: you will set the technical direction for package-level SI/PI across advanced packaging platforms (CoWoS, EMIB, 3D die stacking) while staying hands-on with modeling, simulation, and post-silicon correlation.
You will own the SI/PI strategy from early architecture through high-volume production, partnering with silicon design, physical design, system architecture, and possible with OSAT/substrate vendors to ensure robust signaling and power delivery across die-to-die, memory, and high-speed SerDes interfaces.
What You Will Do
• Lead and develop a team of SI/PI engineers, setting priorities, driving career growth, and building world-class packaging expertise.
• Define and execute SI/PI design methodology for 2.5D/3D IC packages—including silicon interposer, RDL, TSV, and bridge-based architectures.
• Drive chip-package-system co-design by performing end-to-end SI/PI analysis and optimization for HBM (HBM3/HBM3E+), PCIe Gen5/Gen6/Gen7, UCIe die-to-die interconnects and high-speed SerDes (112G+/224G PAM4).
• Own PDN design and sign-off across die, interposer, package substrate, and PCB, including AC/DC/transient droop analysis and decoupling strategy.
• Develop and validate channel models (S-parameter, IBIS-AMI) and perform BER/eye-diagram analysis for multi-lane high-speed links.
• Establish SI/PI design guidelines, sign-off criteria, and automation flows; drive continuous improvement in accuracy and productivity.
• Partner with ASIC architects, PHY/IP teams, package layout, thermal/mechanical, PCB, and system design teams to close electrical specifications.
• Collaborate with other internal partners and external partners (possible like foundry, OSAT, and substrate suppliers etc.) on technology assessment, DFM trade-offs, and new package platform enablement.
• Lead post-silicon validation and model-to-hardware correlation using VNA, TDR, oscilloscope, and spectrum analyzer measurements.
Required Qualifications
• MS or PhD in Electrical Engineering, with emphasis in electromagnetics, signal integrity, power integrity, or microelectronics.
• 12+ years of progressive SI/PI engineering experience in semiconductor packaging (IC package, interposer, or substrate design).
• 3+ years of direct people-management experience leading SI/PI or packaging engineering teams.
• Demonstrated expertise in 2.5D/3D advanced packaging technologies (CoWoS-S/L/R, EMIB, Foveros, 3D die stacking, TSV, RDL, flip-chip BGA).
• Hands-on experience with SI/PI analysis for high-speed SerDes interfaces at 56G NRZ / 112G+ PAM4 data rates.
• Strong background in HBM3/4 SI/PI design and timing budget methodology (HBM3/HBM3E/HBM4 or newer).
• Experience with PCIe Gen5/Gen6 channel design, compliance, and sign-off at the package and system level.
• Working knowledge of UCIe or comparable die-to-die interconnect standards for chiplet architectures.
• Proficiency in industry EDA/simulation tools: Ansys HFSS/SIwave/Q3D, Cadence Sigrity (PowerSI, SystemSI), Keysight ADS, HSPICE/Spectre.
• Strong scripting skills (Python, MATLAB, Tcl) for simulation automation and data analysis.
• Proven ability to drive cross-functional alignment across silicon, package, board, and system teams in a fast-paced product environment.
Preferred Qualifications
• Experience with PCIe Gen7, 200G/400G Ethernet SerDes, or NVLink-class ultra-high-speed interconnects.
• Expertise in UCIe advanced (UCIe 2.0) protocol-level SI/PI considerations and latency-sensitive chiplet integration.
• Familiarity with next-generation HBM standards (HBM4e) and associated PHY/package co-design challenges.
• Track record of new product introduction (NPI) from concept through high-volume manufacturing.
• Experience with on-die EMIR/DVD analysis and chip-package PDN co-simulation workflows.
• Exposure to EMI/EMC analysis and mitigation at the package and system level.
• Knowledge of thermal-aware SI/PI design—understanding package warpage, material Dk/Df drift, and reliability impacts on signal performance.
• Experience evaluating emerging packaging platforms (glass substrate, hybrid bonding, fan-out panel-level packaging).
• Active participation in industry standards bodies (IEEE, UCIe Consortium, JEDEC, OIF).