Sr. Principal Layout Designer

• Custom IC Mask/Layout design for 40/22nm/other Analog, RF, and mixed/signal circuits.

• Lead end to end layout development for any blocks/IP/chip from concept to tapeout.

• Provide technical guidance on floorplanning, placement, routing, shielding, matching, and layout optimization techniques.

• Work closely with the junior engineers’ and contractors’ team for scheduling tasks, guiding them in the floor planning of blocks, implementation, reviews, and closure.

• Work closely with design engineers and CAD support by maintaining effective communication.

• Review and approve layouts for quality, DRC/LVS/PEX closure, EM/IR compliance, ESD robustness, and manufacturability.

• Develop methods to improve efficiency in layout methodology and drive best practices for a quality, reliable and timely outputs.

• Bachelor / Master’s Degree with 10-12 years of relevant experience

• Strong proficiency in using Cadence Virtuoso XL for layout and Calibre for DRC/LVS/PEX.

• In‑depth understanding of CMOS IC mask design and verification, with solid knowledge of fabrication, electromigration, IR drop, coupling capacitance, device and signal matching, and Layout‑Dependent Effects (LDE).

• Self‑driven professional with effective planning and reporting capabilities.

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