Sr. SRAM Layout Design Engineer supporting Nvidia
Posted
Sustainable Talent is partnering with NVIDIA, a global leader that has been transforming computer graphics, PC gaming, and accelerated computing for over 25 years. We are looking for a Senior SRAM Layout Design Engineer to support our client's team onsite in Santa Clara, CA.
This is a full-time (W-2) contract role. We offer competitive pay $110/hr - $120/hr based on factors like experience, education, location, etc. and provide full benefits, PTO, and amazing company culture!
What you'll do:
- Manage the complete custom layout process for SRAM (Static Random-Access Memory) bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
- Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
- Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.
- Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tape out.
- Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.
- Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
- Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
- Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
- Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.
Key required skills:
- Have a BSEE or equivalent experience
- 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.
- Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.
- Solid grasp of SRAM and memory layout principles.
- Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.
- Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.
- Experience with floor planning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.
- Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.
- Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams.
- Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.
- Knowledge of layout automation or AI tools is a definite plus.
Sustainable Talent is a M/F+, disabled, and veteran equal employment opportunity and affirmative action employer.
Skills
As published by greenhouse · 14 questions · 1 written answer
Basics
First Name, Last Name, Email, Phone, Resume/CV, Cover Letter, Location
Short answers (6)
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- What are your compensation expectations?
- Have you been referred by someone? If so, please provide the referrer's name below. optional
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- Please confirm the city and state you currently reside in and the work type you're open to- Onsite, Hybrid, and/or Remote.
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- Are you authorized to work in the U.S. without the need for current or future visa sponsorship (including H-1B), transfer, or third-party arrangements (e.g., C2C or C2H or 1099)? We are unable to offer sponsorship or third-party contracts for this position.
- Do you have 5+ years of hands-on experience specifically in SRAM, memory compiler, or full-custom memory IP layout?
- Have you worked hands-on with FinFET or GAA-based custom layout at 5nm, 3nm, or smaller?
- Do you have extensive hands-on experience using both Cadence Virtuoso (layout creation) and Calibre or ICV (DRC/LVS/ERC debugging)?
- Have you personally owned end-to-end floor planning and/or physical verification for an SRAM or memory macro (not just bitcell-level work)? optional
- Do you currently live a commutable distance from Santa Clara, CA and able to work onsite 5 days a week?
Written answers (1)
- Please describe how your experience aligns with this position and highlight any key skills or accomplishments.