STA Engineer

Job Description:

Synthesis, static timing analysis, timing closure, and equivalency checking
- Should be very comfortable writing scripts in TCL and Perl to achieve higher performance and productivity through automation
- Work very closely with logic designers and physical design engineers (all members of the same group) to build complex SOC's

Job Requirements:

- BSEE with 12+ (or MSEE with 9+) years related experience;

- Extensive timing analysis experience using PrimeTime
- Experience generating timing constraints from scratch for block and top levels
- Formal equivalency checking using LEC or Formality

- Experience with 45nm or later technology
- Low power design methodology and DFT knowledge is a plus