Staff Engineer/ Technical Manager, Physical Verification CAD

Job Description

• Co-work with PDK team to code and maintain DRC / LVS / ANT / ERC / LPE / ESD rule deck for various processes
• Develop layout implementation flow and physical verification flow
• Co-work with QA team to reduce the PDKs/Rule deck defect
• Perform full-chip physical verification such as debugging DRC / LVS / ERC
• Implement automation scripts in C-shell, Python and Perl

Job Requirements

• Bachelor/Master’s Degree in Electrical / Electronics Engineering / Computer Science
• With a min. 8 years of relevant experience in IC Design Industry
• Familiar with IC Design front-to-backend flow
• Familiar with interposer design, TSV technology and chip stacking techniques such as
• CoWoS or EMIB with 2.5D and 3D ICs experiences. (Must have)
• Preferably well-versed in Calibre, ICV
• Proficient in script programming, such as, Tcl, Perl or C-shell
• Proficient in UNIX (Linux) platforms
• Strong communication skills, problem solving and analytical skills

Interested candidates may apply through the application system. Shortlisted candidates will be notified.

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