Technical Manager of Digital Design

1. 4/5/6G modem hardware architecture and digital circuit design task
2. Define hardware architecture of a digital IP/system
3. Include Clock, Bus (AXI/APB/NOC/…), Async design, high speed IF, new IP for sub-sys design topic
4. IP and Subsys digital design and PPA optimization
5. Subsys integration from RTL to gate level including timing closure and testability
6. Design methodology and integration flow improvement

#LI-LL1

1. Have some experiences in computer architecture, digital design topic and flow ( Architecture design, RTL Coding, design Integration, verification, PPA optimization)
2. Familiar with front-end or back-end implementation flow and related EDA tools
3. Better to have experience in clock tree structure and power analysis flow
4. Better to have experience in SoC platform architecture including MCU, Bus, Cache, clock , reset and debug system
5. Better to have experience in chip integration task
6. Better to have knowledge about 4/5G Modem User Plane System, IP Layer Function