[新竹]SOC Physical Designer(APR)

SOC-PD team is hiring both junior and senior engineers, whose work scope is physical design from netlist to GDS: P&R, design quality check, partitioning, timing analysis/fixing/signoff, DRC, LVS, IR, also all related flow.

Join us, you will work together with expertise in all these areas; you will not only work for physical design, but also enjoy and experience for all related products: smart phone/ tablet/ wearable/automotive etc.; you will work for the most advanced process/technology, the best chip in the world.

What you'll be doing:

• P&R implementation
• Floorplan, Powerplan, Place, CTS, Routing, Physical Verification and IR drop analysis
• Co-work with PI engineers to implement chip partition and floorplan
• Work in conjunction with PI engineers to achieve timing closure for both partition and full chip level
• Flow automation development, Methodology in any of above areas.

What we need to see:

• BSEE, MSEE is preferred
• Project experience in IC design implementation
• Courses taken in digital design, physical design
• Hand-on experience in EDA software from Synopsys (ICC2/FC/ICV), Cadence (Innovus), Ansys(RH/RHSC) is preferred

Ways to stand out from the crowd:

• Proficient user of Perl, Python or TCL is preferred
• Excellent English communication skill