[新竹]SOC Physical Designer(IR/EM)

SOC-PD team is hiring both junior and senior engineers for IR/EM signoff and methodology development. The scope includes IR/EM analysis and execution, power integrity architecture design, and flow/methodology optimization for advanced SoC products.

Join us, and you will collaborate with experts across physical design, power integrity, and signoff domains. You will contribute to the development of cutting-edge chips for smartphones, tablets, wearables, automotive, and more—using the most advanced process nodes and technologies in the world.

What you'll be doing：

• Execute IR/EM analysis and signoff for full-chip and partition level
• Develop and maintain power mesh architecture and power planning strategies
• Optimize IR/EM flow and methodology for accuracy, runtime, and scalability
• Collaborate with physical design and PI teams to ensure power integrity across partitions
• Drive correlation and validation between early IR estimation and final signoff
• Support EDA tool evaluation and customization for IR/EM signoff
• Develop automation scripts and dashboards for IR/EM reporting and debugging
• Participate in cross-functional reviews to ensure robust power delivery network (PDN)

What we need to see：

• BSEE or MSEE is preferred
• Solid understanding of power integrity concepts: IR drop, EM, PDN design
• Experience with IR/EM signoff tools such as Ansys RedHawk/RedHawk-SC, Voltus
• Familiarity with physical design flow and constraints
• Knowledge of advanced process node challenges (e.g., FinFET, 3nm/5nm)

Ways to stand out from the crowd：

• Experience in developing IR/EM methodology or flow automation
• Strong scripting skills in Python, or TCL
• Familiarity with power grid modeling and early IR estimation techniques
• Excellent problem-solving and communication skills
• Passion for innovation and continuous improvement