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Leads hardware manufacturing and operations for AI connectivity products, partnering with Asian contract manufacturers to scale production of cables, modules, and chassis systems while optimizing quality, cost, and time-to-market.
Hardware Lab Engineer at Astera Labs in San Jose sets up and maintains test environments for silicon validation of AI connectivity solutions like PCIe, CXL, and Ethernet, using high-speed test equipment and Python automation.
Designs and implements high-performance semiconductor chips for AI infrastructure, focusing on physical design flows, signoff, and automation in advanced process nodes.
Principal Digital Design Engineer at Astera Labs designing high-performance AI connectivity silicon, owning RTL implementation through silicon bring-up for PCIe, CXL, and other protocols.
Principal Digital Design Engineer at Astera Labs designing high-performance connectivity solutions for AI infrastructure, using RTL, synthesis, and advanced CMOS nodes.
Designs high-performance digital blocks for AI infrastructure chips, using Verilog/SystemVerilog and EDA tools to solve data bottlenecks in semiconductor connectivity solutions.
Senior Principal Digital Design Engineer at Astera Labs in San Jose, CA, leading architecture and RTL implementation for AI connectivity chips using PCIe, CXL, UALink, Ethernet, and DDR protocols.
Designs power integrity and electromigration checks for AI-focused semiconductor chips, using tools like Ansys RedHawk and Cadence Voltus to ensure reliability in advanced FinFET nodes.
Designs power integrity and electromigration solutions for high-performance AI chips, ensuring voltage stability and reliability in advanced semiconductor nodes.
Junior Physical Design Engineer at Astera Labs in Tel Aviv builds and optimizes semiconductor chips for AI infrastructure, focusing on physical implementation, signoff, and automation using RTL-to-GDS flows and EDA tools.
Leads a team to verify next-generation AI infrastructure SoCs using UVM, formal methods, and emulation, ensuring first-pass silicon success for complex designs in compute and networking.
Leads cross-functional ASIC development programs from planning through tapeout, coordinating RTL design, verification, physical design, and external partners to deliver custom silicon for AI infrastructure.
Leads SoC design for high-performance connectivity chips, owning RTL, synthesis, timing closure, and pre/post-silicon debug at advanced process nodes using Synopsys/Cadence tools.
Leads timing closure and sign-off for high-speed connectivity ASICs at Astera Labs, using advanced STA tools and methodologies for 7nm+ SoCs in AI infrastructure.
Principal Analog Design Engineer at Astera Labs designs high-performance analog and mixed-signal circuits for AI connectivity hardware in San Jose, CA.
Leads ASIC design for AI infrastructure connectivity, focusing on Ethernet, PCIe Gen 6/7, and UALink. Sets technical direction, mentors engineers, and drives hardware/software integration for high-speed networking and AI interconnects.
Lead ASIC design for high-speed Ethernet and AI interconnect fabrics, defining architecture and RTL for controllers, NICs, and packet processing pipelines to enable rack-scale AI infrastructure.
Designs and implements RTL for high-speed interconnect silicon (PCIe, CXL, Ethernet) that powers AI infrastructure, shepherding blocks from spec to tapeout.
Leads end-to-end physical design of high-performance AI infrastructure SoCs, owning floorplanning, timing, power, and signoff for advanced process nodes (7nm+) while mentoring engineers and collaborating with RTL, DFT, and analog teams.
The Hardware Validation Technician will work onsite in a manufacturing environment to assemble products, operate production equipment, and support engineers in testing and validating new processes. The role requires strong attention to detail and the ability to follow standard operating procedures to ensure product quality and safety.
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