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Sr. Principal Program Manager, ASIC Design
Leads cross-functional ASIC development programs from planning through tapeout, coordinating RTL design, verification, physical design, and external partners to deliver custom silicon for AI infrastructure.
Hardware Lab Engineer
Hardware Lab Engineer at Astera Labs in San Jose sets up and maintains test environments for silicon validation of AI connectivity solutions like PCIe, CXL, and Ethernet, using high-speed test equipment and Python automation.
Principal Physical Design Engineer
Designs and optimizes physical layouts for AI connectivity ASICs using EDA tools like Cadence/Synopsys, ensuring timing closure and signoff for complex SoCs in server/storage/networking applications.
Hybrid Hardware Data & BOM PLM Engineer (Teamcenter)
Maintains and quality-checks electronic component data across a hardware development organization: manages component databases, performs BOM analysis, and supports engineering teams with component selection and qualification, ensuring data integrity in PLM systems such as Teamcenter.
Program Director - Hardware Systems (All Genders)
Program Director who owns a major hardware defence program end to end — from early R&D through production readiness — co-leading with a Chief Engineer, building and scaling a multidisciplinary engineering team, and coordinating across engineering, manufacturing, supply chain, and business functions at a defence technology company.
RTL Design Engineer (ASIC/SOC)
Leads RTL design, simulation, and verification for ASIC/SoC products: integrating and validating IP blocks, optimizing power/performance/area trade-offs, and working with backend teams through tapeout and post-Si testing. Core stack: Verilog/SystemVerilog, VCS/Verdi, AMBA APB/AXI, RISC/Arm architectures. Posted via an HR staffing agency.
FPGA Design Engineer- Cisco Silicon One
FPGA design engineer on Cisco's Silicon One team, owning FPGA development for next-gen networking and AI infrastructure hardware — from architecture and RTL design (Verilog/SystemVerilog) through synthesis, timing closure, and lab bring-up/validation, including high-speed interfaces like PCIe, Ethernet, and SerDes.
Senior Control Electronics Engineer
Designs flight-critical control electronics for hypersonic vehicles: motor controllers, actuator drivers, and mixed-signal circuits, owning PCB design through bring-up, validation, and production readiness. Tooling spans Altium, SPICE, MATLAB/Simulink, ARM MCUs, CAN, FPGA, and embedded C. On-site in Rio Rancho, NM.
Hardware Engineers: RTL Implementation and Evaluation Workflows
Not a traditional job: a paid remote research study where hardware engineers walk Terac researchers through their RTL design, implementation, and verification workflows in a screen-shared interview and give feedback on evaluation tooling. Targets ASIC, FPGA, verification, and SoC experts; pays $147/hour.
Projektleiter - Eplan / Hardware / Automotive (m/w/d)
Project lead (m/w/d) at Morath Automatisierung GmbH in Titisee-Neustadt, Germany: leads hardware/electrical engineering projects using Eplan for automotive automation. Day to day: developing hardware concepts with customers for production lines, transport systems and special machinery; part of the ROFA Group.
Hardware Qualification System Engineer
System engineer on Innoviz's Hardware Qualification team who coordinates hands-on functional and reliability testing of LiDAR systems, analyzes test data with Python/Matlab or AI tools, drives failure-analysis cycles with R&D groups, and reports results to stakeholders, per automotive standards. On-site in Rosh Ha'Ayin, Israel; employed via a third-party provider.
Mechanical and Electronics Engineer
We are seeking a talented Mechanical and Electronics Engineer to join our team in Maharashtra. This role is ideal for individuals who have a diploma in mechanical engineering or electronics engineering and are eager to…
商业分析师（存算与AI） - 芯片研发
团队介绍：聚焦存算一体芯片设计，主要围绕AI大模型应用场景进行高能效计算技术创新，设计多款基于存算一体架构的高能效AI芯片，突破传统冯・诺依曼架构下的 "内存墙" 瓶颈，提升能效比、降低算力成本。团队具备独立流片与量产落地能力，累计申请专利近300项，核心专利覆盖“底层器件-核心架构-工程落地”全流程。同时与字节各团队算力需求整体协同，更好的发挥存算一体芯片的技术价值，共同为AI业务提供高能效算力底座。…