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As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and…
Worker Type: EmployeeJob Post End Date: 09/18/2026 About this opportunity: The Senior Subsea Hardware Engineer provides technical stewardship, integrity management, and system coordination for subsea production…
About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI,…
Job descriptions may display in multiple languages based on your language selection. What we offer: At Magna, you can expect an engaging and dynamic environment where you can help to develop industry-leading automotive…
University - Summer 2027 Electronic Warfare FPGA Engineering Intern The Opportunity: Join a team developing advanced capabilities in electronic warfare and software defined radio systems. As an FPGA Engineering Intern,…
Retail Sales Manager at Busy Beaver, a neighborhood home improvement (lumber/hardware) store: oversees day-to-day store operations in the GM's absence, drives sales and customer engagement, manages merchandising, inventory and budgets, and coaches staff.
Own and build hardware-in-the-loop test infrastructure for satellites, automating test orchestration with Python/C/C++ against real or emulated spacecraft hardware in a lab environment.
Designs and implements FPGA/RTL logic for satellite compute payloads, including sensor interfaces, DDR/DMA datapaths, and ARM SoC integration, to support orbital data and energy systems.
First-line on-site support for Genius Sports' Dragon tracking systems and video streaming hardware at sports venues: maintaining, troubleshooting, and replacing cables, cameras, and network devices before and during live events, working independently with remote engineering backup, with weekend/match-day availability.
About the Team The Consumer Products team at OpenAI builds the hardware that brings advanced AI technology directly into people’s hands. We design, engineer, and manufacture next-generation consumer devices that…
Sanderson is working in partnership with a leading global provider of ICT Services for the large enterprise and public sector markets. We have several Permanent opportunities for Field Services Engineers based across…
Intern designs and optimizes high-performance CPU and AI chips, working through synthesis to tapeout using tools like PnR and timing analysis.
Own synthesis and place-and-route for high-speed CPU chiplets in advanced AI silicon using Synopsys/Cadence tools.
Leads a team of Verification Engineers to shape test strategies for AI hardware, validating functionality and performance of AI cores. Core technologies include AI-specific data types, compute patterns, on-chip network validation, UVM, SystemVerilog, and cocotb.
Director leading customer-facing hardware engineering at Tenstorrent, owning technical relationships with strategic customers and FAEs to translate silicon needs into RTL/verification specifications for custom AI silicon programs.
Designs and implements high-performance CPU and AI/ML chip blocks from synthesis to tapeout, optimizing power, performance, and area using advanced EDA tools and methodologies.
Physical Design Engineer owning Die-to-Die interface implementation from RTL to GDSII for advanced-node chiplet architectures, using full PD flow (synthesis, P&R, CTS, sign-off) with Synopsys/Cadence/Mentor EDA tools and Tcl/Python automation.
Designs and implements high-performance AI SoC partitions from synthesis to tapeout, focusing on timing, power intent, and physical verification using Synopsys tools (Design Compiler, Fusion Compiler, IC Compiler II).
Drive static timing analysis and closure for high-performance RISC-V CPUs and AI SoCs, collaborating with logic, DFT, and physical design teams using STA tools, SDC constraints, and Python/Perl/TCL scripting.
Implement physical design for RISC-V CPUs and AI architectures, owning the flow from synthesis to tapeout to optimize performance, power, and area.
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