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Own and ship reliable electronics for unmanned surface vehicles, balancing power, communications, and payload systems while debugging hardware in demanding, remote environments.
Design verification engineer building silicon IP for Google’s AI accelerators and infrastructure, using SystemVerilog/UVM to verify ASIC blocks and close coverage for tape-out.
Designs analog and mixed-signal circuits for automotive ICs, ensuring compliance with strict requirements and supporting layout/testing.
Leads hardware quality initiatives, analyzes reliability data, and drives supplier improvements to ensure smooth product transfer to manufacturing.
Designs high-voltage battery management hardware for electric vehicles, including schematics, simulations, validation, and testing while adhering to automotive safety standards.
Leads the development of Samsara's hardware products, coordinating engineering, design, and manufacturing to deliver IoT devices for fleet and industrial operations.
#WeAreIn for jobs that impact everyone's life. Join the thinkers, builders, and problem-solvers behind tomorrow’s technology. As a Senior Test Hardware Engineer, you'll have the opportunity to merge creativity…
Leads power-electronics hardware development for industrial rectifiers and UPS systems, coordinating cross-functional teams to meet specs and timelines.
Design and test RF hardware (transmitters, receivers, exciters) for radar and datalink systems, using tools like ADS and HFSS, while meeting strict mechanical and environmental constraints.
Senior Hardware Engineer designing complex circuits and PCBs for Allegro’s semiconductor products, mentoring junior engineers, and driving design best practices from concept to production.
Lead hardware development for power conversion products like rectifiers and UPS systems, coordinating cross-functional teams to meet specs and timelines.
Senior engineer designs and optimizes low-power SoCs, focusing on physical verification, EM/IR drop analysis, and power integrity using tools like Cadence Innovus and Voltus.
Design and verify mixed-signal ASICs and ROICs for image sensors, including analog signal chains, low-power ADCs, and system-level simulations using Cadence, MATLAB, and Python.
Design and validate rack-level network interconnect hardware for AWS, owning the full lifecycle from concept to manufacturing and operations using Python test automation and cross-functional collaboration.
Senior ASIC engineer designing on-chip interconnects and last-level caches for NVIDIA’s CPU and AI platforms, focusing on synthesis, timing closure, and performance optimization.
Develops C++ tools and automated workflows for RTL generation and ASIC design at NVIDIA, improving Verilog RTL quality and connectivity algorithms for GPU and AI hardware.
Designs and verifies GPU and control subsystems for AI-focused SoCs, integrating Arm IP and third-party components for edge, physical, and cloud AI applications.
Senior engineer who implements custom IP and SoC designs from RTL through GDSII, closing timing, optimizing power, and signing off on next-gen FPGA silicon using Synopsys/Cadence EDA tools.
Senior Hardware Technician builds, configures, and tests Oracle server hardware in a lab, performing PCB rework, system bring-up, and validation while maintaining lab readiness and collaborating with engineers.
Design and develop FPGA solutions for wireless communications systems, guiding projects from requirements through implementation, integration, and testing.
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