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Who We Are Applied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment…
Are you a problem solver looking for a hands-on internship position with a market-leading company that will help develop your career and reward you intellectually and professionally? About Analog Devices Analog…
An internship supporting the production of surgical robot hardware for brain-interface devices, focusing on assembly, process optimization, and quality control in a high-precision medical manufacturing environment.
Designs low-power digital circuits for brain-computer interfaces, including processors, accelerators, and radio components, using SystemVerilog, C/C++, and Python.
Designs and tests analog/mixed-signal integrated circuits for brain-machine interfaces, focusing on low-power, compact solutions using advanced CMOS FinFET technologies.
Undergraduate internship at Solidigm supporting hardware design, evaluation, debug, and new product development for data center SSDs. Interns assist with schematic reviews, board bring-up, test data analysis, and Python-based automation across cross-functional engineering teams.
Graduate internship at Solidigm supporting data center SSD products across electrical validation, hardware bring-up, signal integrity, and product engineering. Interns execute test plans, use lab equipment (oscilloscopes, protocol analyzers), debug PCIe and system issues, and analyze performance, power, and reliability data, often with Python and Linux.
An intern on NVIDIA's SOC Design Methodology team in Shanghai will analyze and improve digital ASIC front-end design flows, then build AI agents and automation scripts (Python/Perl, LLM-based tooling) to speed up and automate chip design work used across NVIDIA's SOC projects.
Microsoft is hiring a Hardware Engineering Intern in Hillsboro, OR to design, develop, and test hardware components for electronic devices, including defining design specifications and developing test plans. Candidates must be pursuing a Computer, Electrical, or Mechanical Engineering degree, with embedded programming and C/C++/C# knowledge preferred.
Graduate trainee RTL design role at AMD in Penang, Malaysia, working on High Speed IO Protocol IPs (USB, PCIe, Ethernet, UFS) used in AMD products. Day to day: running design flows, simulations and regressions, first-level debugging of design/test errors, and scripting to automate tasks. Core skills: SystemVerilog/Verilog, Perl, TCL, Python.
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative…
The NVIDIA SOC group is looking for ASIC Design and Verification Interns to join the SysASIC and Clock teams. In this position, you will participate in the design and verification of complex reset/fuse/ism/sysctrl/boot…
Date Posted: 2026-09-03

 Country: United States of America

 Location: US-AZ-TUCSON-M02 ~ 1151 E Hermans Rd ~ BLDG M02

 Position Role Type: Onsite

…
Job Description Summary Addressing the climate crisis is an urgent global priority, and at GE Vernova, we take our responsibility seriously. That is the singular mission of GE Vernova: to continue electrifying the…
University - Summer 2027 Electronic Warfare FPGA Engineering Intern The Opportunity: Join a team developing advanced capabilities in electronic warfare and software defined radio systems. As an FPGA Engineering Intern,…
Intern designs and optimizes high-performance CPU and AI chips, working through synthesis to tapeout using tools like PnR and timing analysis.
A Masters-level silicon design engineering intern at AMD in Austin, TX, working full-time onsite from September to December 2027. The intern supports new product bring-up, debugs silicon issues, develops diagnostic firmware for IP training/margining, and improves test automation using Python/Perl on Unix/Linux plus lab equipment like oscilloscopes and BERTs.
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