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Senior Data Engineer on Tabby's Data Services team, building internal data products such as a Feature Store, developing EL/ELT/ETL pipelines, and integrating new data processing and storage tools. Core stack: Python, SQL, Airflow, Debezium, BigQuery/ClickHouse, PostgreSQL/CockroachDB, Docker, GitLab CI/CD, and GCP.
Vizzia, a French post-Series B scale-up providing security camera solutions to local authorities, is hiring its first UK Security Project Manager in London. The role leads end-to-end rollout of camera installations for councils, trains and manages installation partners, conducts site surveys, and serves as the technical point of contact for clients, with regular UK-wide travel.
Remote Project Manager for international e-commerce and marketing projects, focusing on process automation, AI implementation, and business efficiency optimization.
Cerebras (maker of the world's largest AI chip) is hiring an Application Security Engineer in Sunnyvale, CA to own its vulnerability management program end to end — discovering, prioritizing, and driving remediation of vulnerabilities across applications, containers, cloud infrastructure, and AI platforms — using automation, SAST/SCA/DAST tooling, and AI agents rather than manual ticket tracking.
Build QA processes from scratch for an AI-powered EdTech school scheduling platform using Python, pytest, Playwright, and AWS to optimize academic and staffing priorities.
🎤 Why voize? Because we’re more than just a job! At voize, we believe the greatest gift to frontline workers is time - time to care, connect, and be present. Today, that time is lost to busywork and complex systems…
A senior ASIC design engineer who designs, verifies, brings up, and debugs digital subsystems in electro-optical SoCs for Ayar Labs' co-packaged optics that move data for AI systems. Day to day: RTL in Verilog/SystemVerilog, testbenches, timing constraints and documentation, and Python-driven silicon bring-up.
Own the firmware development lifecycle for Ayar Labs' co-packaged optics products in Bengaluru (on-site): designing and optimizing bare-metal embedded C firmware for electronic-photonic chips with high-speed SerDes, driving silicon bring-up and hardware validation, and mentoring junior engineers.
Senior hardware/embedded engineer at Ayar Labs in Hsinchu designing embedded electronics and laser driver architectures (control loops, monitoring firmware) for co-packaged optics that move data for AI systems. Day to day: analog/digital schematic capture and PCB layout support, component integration, hardware bring-up and debugging, and cross-functional work with optics, packaging, and manufactur
Writes Python software to automate hardware test runs, data analysis, and instrument control for Ayar Labs' optical interconnect chips (SuperNova, TeraPHY), enabling high-volume production. Works with instrument drivers, test recipes, Git/CI-CD, and MongoDB/PostgreSQL in a startup test engineering team.
Ayar Labs is hiring a hands-on ASIC engineer to design, verify, and bring up digital subsystems in electro-optical SoCs for its co-packaged optics products that move AI data over light. Day to day this means writing Verilog/SystemVerilog RTL, building testbenches, defining timing constraints, and debugging custom silicon with Python and firmware.
Principal AMS engineer at Ayar Labs will architect the high-speed optical PHY (TX, RX, clocking, mixed-signal control loops) for next-gen co-packaged optics products serving AI data centers, set the analog/mixed-signal technical direction, and lead first-silicon success, debug, and mentoring. Core tech: advanced FinFET CMOS, Cadence ADE/Spectre, SerDes-class AMS design.
Senior embedded firmware engineer at Ayar Labs who owns the firmware lifecycle for co-packaged optics products — designing control firmware for electronic-photonic chips with high-speed SerDes, mentoring engineers, and collaborating across hardware, software, and validation teams. Core stack: bare-metal C on microcontrollers/ARM, Git, JIRA, CI/CD.
Ayar Labs is hiring a Senior Embedded Firmware Engineer in San Jose to design, test, and bring up bare-metal C firmware that controls high-speed SerDes interfaces and photonic subsystems in its co-packaged optics products for AI data infrastructure. The role spans firmware architecture, unit/integration testing, CI/CD, and first-silicon debugging.
A senior photonics design engineer at Ayar Labs designs, simulates, and characterizes integrated photonic components (couplers, gratings, micro-ring resonators) for the company's co-packaged optics AI infrastructure products. Day to day: device design, test-vehicle planning and measurement-driven iteration, building Python simulation/analysis tooling, and collaborating across packaging, laser, cir
Ayar Labs is hiring a Senior Principal Engineer, SoC Architect in San Jose (on-site) to define next-generation SoC architectures for high-performance semiconductor products — leading high-speed I/O integration (PCIe, CXL, UCIe, SerDes, Ethernet), performance/power modeling, and cross-functional technical leadership from concept through silicon realization.
Design analog/mixed-signal IC blocks (oscillators, high-speed transmitters/receivers, ADCs/DACs, biasing circuits) for Ayar Labs' co-packaged optics, on-site in San Jose. Work spans Cadence-based design and sign-off simulation on FinFET CMOS at 50+ Gb/s, plus post-silicon bring-up in the lab.
Sr. Staff Engineer designing and debugging digital subsystems for Ayar Labs' electro-optical ASICs (co-packaged optics that move AI data over light). Day to day: writing RTL in Verilog/SystemVerilog, building testbenches, defining timing constraints, and doing silicon bring-up/debug with Python, C/C++, and firmware — on-site in San Jose.
Ayar Labs is hiring a Sr. Staff Embedded Firmware Engineer in San Jose (on-site) to design bare-metal C firmware controlling high-speed SerDes and photonic subsystems, from architecture through silicon bring-up and customer deployment. The role involves unit/integration testing, CI/CD, and close collaboration with analog, digital, photonic, and validation teams.
Ayar Labs is hiring a Sr. Staff Engineer, Photonics Design in San Jose to own the photonic device layer of its co-packaged optics solution for AI data movement — setting device performance targets, working with Taiwan foundries on process capability, and building simulation/layout/verification infrastructure. Core skills: silicon photonics device design, FDTD/charge transport simulation, and Pytho
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