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About the Company Retym is an innovative semiconductor startup developing next-generation chips for high-speed communication systems. Our mission is to redefine performance and efficiency in data transmission through…
The Staff/Sr Staff Engineer will lead RTL design and micro-architecture development for complex IP and subsystems within Renesas MCU products. The role involves collaborating with cross-functional teams to ensure PPA targets are met using industry-standard EDA tools.
The Principal Engineer will lead RTL design and micro-architecture development for complex IP and subsystems within MCU SoCs. The role involves collaborating with cross-functional teams to ensure PPA targets are met while mentoring junior engineers and improving design methodologies.
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
Design Verification Engineer at Cisco Acacia tests and automates verification of photonic integrated circuit (PIC) devices, debugs new optoelectronic components, and improves production yields using Python, RF/EO testing, and coherent optical methods.
ASIC Design Engineer working on mixed-signal chips for GPU power delivery and management, defining micro-architecture and developing RTL behavioral models through the full ASIC design flow to tape-out.
Designs and verifies PCIe controllers for NVIDIA’s GPUs/SOCs using UVM/Specman/e, building reusable testbenches and ensuring correctness via coverage-based methodologies.
The Senior Staff Digital Design Engineer will lead the design, implementation, and verification of DSP algorithms and digital control logic for audio processing within ASIC systems. This role involves the full ASIC design flow, from specification to silicon bring-up, utilizing expertise in digital signal processing and mixed-signal integrated circuits.
Designs and develops FPGA-based digital solutions for aerospace/defense systems, including RTL architecture, verification, timing closure, and system integration. Works in Agile teams, mentors junior engineers, and collaborates on mission-critical hardware projects requiring security clearance.
A Technical Project Manager ensures efficient, compliant project setups for engineering teams at ARM, coordinating infrastructure, vendor contracts, and governance processes across global stakeholders. Core focus: SOC/ASIC environments, IP compliance, and process automation.
Designs and develops complex ASIC modules for high-performance networking chips, focusing on architecture, RTL implementation, verification, and power/performance optimization. Leads cross-functional teams and mentors junior engineers.
The ASIC Design Engineer will develop high-speed networking chips from specification to netlist, working on micro-architecture, RTL implementation, and timing closure. The role involves collaborating with verification and physical design teams to ensure high-performance silicon for networking hardware.
Design high-speed networking ASICs from spec to netlist using Verilog/SystemVerilog, work with physical design for timing closure, and collaborate with verification teams.
Engineering Project Manager coordinating ASIC development programs at Cisco Silicon One, tracking milestones/risks, and building AI-powered project tracking and automation tools.
Build and maintain end-to-end FPGA design flow automation infrastructure (RTL to bitstream) using EDA tools and Python/Perl/Shell scripting, while applying AI solutions to improve chip design productivity.
Designs and implements high-speed ASIC interconnect silicon, writing RTL and firmware to control analog blocks and ensure hardware-software integration through synthesis, emulation, and silicon bring-up.
Designs and documents medium-to-complex FPGA modules for space applications (robotics, radar, telecom, DSP) by writing VHDL, synthesizing designs, and supporting verification/testing in a lab environment.
Own the end-to-end silicon program for Anthropic’s custom hardware powering Claude, coordinating ASIC design, foundry, and post-silicon bring-up while building lightweight execution systems.
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML…
Develops memory controller firmware for AI, ML, supercomputing, and graphics accelerators in data centers, collaborating with RTL design, DV, emulation, platform, and software teams.
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