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Designs and optimizes next-gen NAND Flash storage systems using FPGA architectures, focusing on RTL development, IP integration, and system validation for high-performance digital solutions.
Staff Digital Design Engineer responsible for all aspects of digital design in 3D NAND Flash memory, including micro architecture, RTL design in Verilog, verification, synthesis, DFT, and timing analysis from RTL to GDSII.
ASIC chip design intern in NVIDIA's Switch Silicon group, working on full-chip design flow automation, verification test facilities, and collaboration across architecture and firmware teams.
Come join Analog Devices (ADI) – a place where Innovation meets Impact. For more than 55 years, Analog Devices has been inventing new breakthrough technologies that transform lives. At ADI you will work alongside the…
Job Details: Job Description: The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in developing and integrating logic designs into complex System-on-Chip (SoC) architectures. Your…
As a Chip Design Engineer at Annapurna Labs, you will own the design of complex hardware blocks for the AWS Nitro system, from microarchitecture definition through to production. You will utilize SystemVerilog and AI-assisted development flows to create high-performance silicon that powers AWS cloud infrastructure.
Design signal processing-intensive RTL for wireless communication SoCs as part of Apple's wireless silicon team, focusing on energy-efficient design and diverse connectivity technologies.
Lead end-to-end digital design and verification for mixed-signal SoCs at the Chandler site, driving strategy, methodology standardization (UVM, formal, AMS/DMS), and team scaling.
Senior Technical Recruiter owning full-lifecycle hardware recruiting (Design Verification, ASIC, physical design, PCB/systems) at an AI chip company, using Greenhouse ATS and sourcing via LinkedIn and GitHub.
Principal AI Silicon Architect designs and optimizes hardware architectures for AI workloads, collaborating with software and hardware teams to deliver high-performance, scalable cloud infrastructure at Microsoft.
Principal engineer designing and verifying custom silicon chips for Microsoft's cloud infrastructure, using C/C++, SystemVerilog, UVM, and Python to ensure hardware quality and performance.
Apple is offering GPU internships in the UK focused on RTL design, power optimization, and physical design for Apple Silicon. Interns will collaborate with engineering teams on chip architecture, power analysis, and ASIC design flows using languages like C++, Python, and Verilog.
About the Company Retym is an innovative semiconductor startup developing next-generation chips for high-speed communication systems. Our mission is to redefine performance and efficiency in data transmission through…
The Staff/Sr Staff Engineer will lead RTL design and micro-architecture development for complex IP and subsystems within Renesas MCU products. The role involves collaborating with cross-functional teams to ensure PPA targets are met using industry-standard EDA tools.
The Principal Engineer will lead RTL design and micro-architecture development for complex IP and subsystems within MCU SoCs. The role involves collaborating with cross-functional teams to ensure PPA targets are met while mentoring junior engineers and improving design methodologies.
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
This role involves designing and maintaining verification plans and SystemVerilog/UVM testbenches for ARM's scalable coherent mesh network interconnects. Engineers will collaborate with architects to debug functional failures and improve verification methodologies for high-performance compute and AI applications.
Designs and verifies high-performance ASIC/SoC chip systems using Verilog/SystemVerilog, UVM, and RTL methodologies in a collaborative engineering environment.
Designs and implements high-performance digital logic for communication and optical networking chips using Verilog/SystemVerilog, guiding the RTL from specification to tapeout while collaborating with cross-functional teams.
Designs and verifies digital circuits for power systems using Verilog, RTL, and FPGA tools, while guiding junior engineers and collaborating with backend teams on synthesis and timing analysis.
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