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Who we are looking for Required Education and Experience B.Tech/M.Tech in Electronics, Electrical Engineering, VLSI, or a related discipline 5+ years of experience in Digital IC Design with strong expertise in RTL…
Principal Physical Design Engineer (STA) at Astera Labs designs and optimizes timing for high-performance connectivity ASICs used in AI infrastructure, leveraging advanced EDA tools and TSMC 7nm processes.
Designs and optimizes ultra-low-latency FPGA hardware for electronic trading systems used by top-tier financial institutions.
Designs, tests, and maintains high-performance FPGA/ASIC systems for ultra-low-latency trading infrastructure, using SystemVerilog for verification and advanced simulation tools.
FPGA Design Engineer responsible for RTL design, development, and optimization of high-performance, ultra-low latency FPGA compute and networking systems for electronic trading infrastructure, primarily using SystemVerilog/VHDL.
The era of pervasive AI has arrived. In this era, organizations will use generative AI to unlock hidden value in their data, accelerate processes, reduce costs, drive efficiency and innovation to fundamentally…
Designs and verifies FPGA systems for defense/aerospace applications using VHDL, focusing on RF/EO DSP, data links, and embedded processing across Xilinx/Microsemi devices.
Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.…
Design and deliver high-performance digital subsystems within mixed-signal ICs, owning the full flow from RTL design through synthesis, P&R, and tape-out using Verilog/SystemVerilog and industry EDA toolchains.
Design and implement embedded systems, hardware, and software for client projects across industries like robotics, consumer devices, and defense, using C, SystemVerilog, PCB design, and more.
Graduate electronics and software engineer designing embedded systems, hardware, and firmware for diverse client projects like robotics, LEGO products, and defense systems.
Build and optimize front-end CAD methodologies and verification flows for Ericsson’s 5G/6G ASICs and FPGAs using SystemVerilog/UVM, EDA tools, and CI pipelines, with a focus on AI-driven automation.
Design verification engineer at Ambiq Micro, Singapore, responsible for verifying low-power SoCs for IoT applications using SystemVerilog/UVM, ARM/RISC-V, and power-aware methodologies.
Senior engineer who designs and runs verification tests for low-power System-on-Chip designs used in IoT and edge-AI products, using SystemVerilog, UVM, and C/C++.
Lead verification of next-gen high-speed interconnect IP and SoC for AI/HPC, defining UVM-based strategies for PCIe, CXL, Ethernet, and UCIe while mentoring teams and driving silicon-level debug.
RF Engineer leading the design, development, and integration of custom radio and RF hardware for national security missions, working across RF, FPGA, digital, and embedded systems at Aberdeen Proving Ground.
Develops and tests electric drive control systems for U.S. Navy submarines using model-based design, MATLAB/Simulink, and hardware/software integration (MIL/HIL/SIL).
The IP Design Verification Engineer ensures the functional quality of Intel's IP designs by developing verification plans, test benches, and simulation environments. The role involves debugging complex logic issues and collaborating with cross-functional teams using SystemVerilog, UVM, and scripting languages like Python or Perl.
This Staff Digital Design Engineer role involves leading the development of digital functions for mixed-signal products, covering the full lifecycle from architecture and RTL design to physical implementation and production maturity. The role requires expertise in SystemVerilog, digital synthesis, and DFT methodologies within a collaborative team environment.
Develops and verifies ASIC/FPGA designs for Boeing’s space and aerospace electronics, focusing on digital ICs, SoCs, and high-performance processors using HDLs, UVM, and simulation tools.
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