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ASIC Design Engineer (Silicon Engineering)

North AmericaFull-time

Designs next-generation ASICs and FPGAs for SpaceX's Starlink satellites and ground infrastructure: RTL design and SoC integration in SystemVerilog/Verilog, power-performance-area optimization, participation in the full design lifecycle, and lab bring-up/validation, collaborating with systems, firmware, architecture, and backend teams.

Asic Bash C++ Firmware FPGA +7 skills

135K – 210K $

Advanced Physical Design and Verification Engineer (7036)

Open 46d HybridInternshipIntern

Overview of Role As a Advanced Physical Design and Verification Engineer, you will be responsible for the Design Rule Check, Layout vs. Schematic checking and fix all PDV/EMIR/Noise/SigEM violations and errors. You may…

Automation Perl Python Rtl Tcl

Principal HS Digital Design Engineer (d/m/f)

Open 46d EuropePrincipal

Principal high-speed digital design engineer at ams OSRAM in Pavia, Italy, working on digital IC design for communication and mixed-signal SoC products: RTL design in Verilog/SystemVerilog, synthesis, timing analysis, clock-domain crossing, and advanced CMOS nodes (FinFET/FD-SOI). Knowledge of UCIe/PCIe interfaces is an advantage.

Cmos PCIe Rtl SystemVerilog Verilog

Senior Staff Digital Design Engineer

Open 46d North AmericaStaff

Senior digital IC design engineer at ams OSRAM's Plano, TX site who designs, verifies, synthesizes, and brings up silicon for sensor/imaging mixed-signal semiconductors. Core stack: Verilog/SystemVerilog, UVM, low-power and CDC/LEC flows, and Cadence tools like Xcelium, Genus, SpyGlass, and JasperGold.

Agile Bash Cadence Virtuoso Perl Python +6 skills

2027 Summer - FPGA Design Engineer Intern - Dallas TX

Open 40d North AmericaInternshipIntern

A 12-14 week onsite summer internship at Leonardo DRS's Dallas facility, supporting the FPGA development team for infrared sensors and systems. The intern helps with RTL coding, testbench development, and FPGA design flows (synthesis, place & route, timing closure, verification); US citizenship and CE/EE enrollment are required.

C++ Cypress FPGA Linux Perl +6 skills

2027 Summer - Digital Design / Design Verification Engineer Intern - Dallas TX

Open 40d North AmericaInternshipIntern

Summer intern on Leonardo DRS's ROIC or FPGA development teams in Dallas, TX, supporting digital IC design for infrared and electro-optical sensor systems. Day-to-day work spans RTL coding, testbench development, synthesis, place-and-route, timing closure, and design verification, with strong mentorship. U.S. citizenship and clearance eligibility required.

C++ Cypress FPGA Linux Perl +6 skills

VLSI Safety Architect

Open 35d HybridEurope

Senior RTL/SoC Functional Safety engineer at Capgemini Engineering in Belgrade: designs hardware in Verilog/SystemVerilog, integrates ISO 26262 safety mechanisms and internal/third-party IPs into complex SoCs, and documents safety requirements through silicon delivery.

AI Embedded Systems Generative AI Iso 26262 Rtl +3 skills

Senior RTL Design Engineer

Open 35d CISSenior

Capgemini Engineering in Kyiv is hiring a Senior RTL Design Engineer with 8+ years of VLSI experience to design and verify complex digital SoC blocks — writing RTL in Verilog/SystemVerilog or VHDL, running CDC/RDC and lint analysis with Synopsys VC Static, and driving designs from specification through tape-out alongside synthesis, STA, and verification teams.

AI Automation Cloud Generative AI Perl +5 skills

AI Accelerator Chip Architect

Senior architecture role at Capgemini in Bangalore leading technical strategy for AI/ML acceleration silicon: defining NPU/Matrix Engine compute architecture, memory hierarchy, and NoC interconnects, while guiding RTL/verification teams and supporting customer workshops. Core stack: ASIC/SoC design, ARM Neoverse/RISC-V compute subsystems, and performance modeling.

AI HPC Machine Learning Rtl

VLSI Safety Architect

Open 35d HybridEurope

Senior RTL/SoC Functional Safety Engineer at Capgemini in Thessaloniki (Greece) who designs and integrates safety mechanisms into complex ASIC/SoC hardware in compliance with ISO 26262. Day-to-day work centers on RTL design in Verilog/SystemVerilog, configuring and integrating IPs, writing safety/integration documentation, and supporting SoC architecture and silicon delivery.

AI Embedded Systems Generative AI Iso 26262 Rtl +3 skills

Senior Digital Designer

Open 35d EuropeSenior

Capgemini is hiring a Senior Digital Designer in Athens to lead functional specification development, microarchitecture, and RTL debugging for high-performance digital/semiconductor blocks, including lint and CDC checks. Core technologies: Verilog/VHDL, SystemVerilog, and synthesis tools like Cadence Genus and Synopsys Design Compiler.

Rtl SystemVerilog Verilog VHDL

Head of Creative Lab | Al- Futtaim Automotive

Open 26d C-level

Job Requisition ID: 181509 About Al-Futtaim Established in the 1930s, Al-Futtaim is one of the most diversified and progressive privately held regional businesses, headquartered in Dubai. Operating across more than 20…

Accessibility AI Analytics E-commerce Figma +8 skills

RTL Design & IP Release Engineer

Supports semiconductor Foundation IP development at Capgemini Engineering in Brasov, Romania: implementing and validating RTL Verilog design changes, running QA checks, and managing ClearCase-based IP release flows with Python automation. Core tech: Verilog/SystemVerilog, ASIC design, CDC/Lint, AMBA protocols, Linux.

AI Asic Automation Cloud Data Science +5 skills

FPGA Engineer - Chip Design

RemoteAPACFull-time

Remote (India) ASIC/FPGA design engineer role building technical evaluations for AI systems: create realistic chip-design tasks, write reference RTL (Verilog/SystemVerilog/VHDL) and testbenches, and review AI-generated designs for functional, timing, and PPA issues using EDA tools from Synopsys, Cadence, Siemens, Xilinx, and Intel.

Agentic AI AI Automation FPGA Perl +8 skills

1.2M – 2M INR

jobs.ametek.com

Staff/Principal Digital Design Engineer

Postition Summary: This position will report to the Director, Engineering and assume engineering responsibility to plan, manage, and oversee detailed sensor design and analysis for custom CMOS image sensors. This…

AI Asic Automation Cmos Firmware +7 skills

careers.ses.com

Senior Engineer, FPGA, MEO 1

Senior Engineer, FPGA, meoSphere ProgramME & Role Description meoSphere is the next generation of SES’s Medium Earth Orbit (MEO) satellites. It will provide secure connectivity services for governments,…

Ethernet Firmware FPGA MATLAB Oscilloscope +7 skills

careers.ses.com

Senior Engineer, FPGA & ASIC System Architecture, meoSphere

Senior Engineer, FPGA & ASIC System Architecture, meoSphere The job responsibilities outlined in this document are not exhaustive and may evolve over time and be reviewed according to business needs. PROGRAMME…

Asic Ethernet FPGA Prototyping Rtl +1 skills

Advanced Micro Devices, Inc

Senior ASIC RTL Design Engineer, AI Networking IP

North AmericaSenior

Senior ASIC RTL design engineer on AMD's IP team building high-performance networking and communications IP cores for AMD chips. Day to day: write synthesizable Verilog/SystemVerilog RTL, leverage AI coding tools for productivity, support synthesis/timing closure, verification regressions, and emulation, and mentor junior designers.

AI Asic Atlassian Bash ChatGPT +14 skills

Advanced Micro Devices, Inc

Memory PHY Principal Design Engineer

North AmericaPrincipal

Seasoned engineer to architect and develop high-speed memory interface IP (LPDDR/DDR) at AMD — defining digital PHY architecture and microarchitecture, leading RTL implementation and firmware integration, and guiding synthesis, timing closure, and power optimization through silicon. Core tech: Verilog/SystemVerilog, UPF, Python/Perl/Tcl.

AI Firmware Perl Python Rtl +3 skills

SambaNova Systems

Senior Hardware Design Engineer

Open 61d North AmericaFull-timeSenior H-1B sponsor history

Designs and owns RTL blocks for SambaNova’s AI-accelerating RDU ASICs, shepherding them from spec to silicon bring-up while optimizing for power, performance, and area.

Agentic AI AI Asic Automation Bash +10 skills

120K – 200K $