Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Digital Design Engineer responsible for SoC/MCU digital sub-circuit development including RTL coding in Verilog/SystemVerilog, synthesis, STA, formal verification, DFT, and post-silicon validation at NXP's Catania site.
Lead the full digital IC design flow for complex SoC microcontrollers at NXP's Catania site, from architecture through RTL coding (Verilog/SystemVerilog), synthesis, STA, formal verification, and post-silicon debug.
This internship role involves assisting with the design, simulation, and verification of digital integrated circuits using Verilog or VHDL. Interns will work on FPGA prototyping, digital modeling, and timing analysis alongside experienced engineers.
Designs and optimizes digital chip backends, focusing on synthesis, DFT, and STA to ensure timing and power closure for large-scale chips.
Job Details: Job Description: About Altera At Altera™, our independence as the world’s largest pure ‑ play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than…
Designs and implements high-performance, low-power ASICs for 5G/6G telecom infrastructure using Cadence and Synopsys tools, focusing on floorplanning, place-and-route, and physical verification.
SyoSil is hiring ASIC/FPGA design and verification engineers to work on RF radio ASIC projects using SystemVerilog and UVM. The role involves full-cycle IP block development, from architecture to verification, within a collaborative, SCRUM-based international team.
Designs and implements high-speed ASIC interconnect silicon, writing RTL and firmware to control analog blocks and ensure hardware-software integration through synthesis, emulation, and silicon bring-up.
The FPGA/Hardware Engineer will design, develop, and verify complex FPGA-based hardware systems for aerospace and avionics applications. The role requires expertise in RTL design, System Verilog/UVM, and hardware validation within regulated environments.
RTL design and integration engineer on AMD's FPGA product team, driving silicon implementation using Verilog/SystemVerilog, EDA tools, and scripting automation.
Leads a team designing and validating high-performance DRAM/HBM memory subsystems for Google’s TPUs, bridging hardware engineering, verification, and ecosystem partnerships to optimize AI infrastructure.
RTL Design Engineer developing TPU (Tensor Processing Unit) silicon for AI/ML hardware acceleration, using Verilog/SystemVerilog to design and verify ASIC blocks.
Design and implement real-time digital signal processing RTL in VHDL/SystemVerilog for Electronic Warfare and SIGINT systems, collaborating closely with RF hardware and embedded software teams.
Architect and implement digital logic embedded in power and analog ICs, owning the full flow from microarchitecture and RTL through synthesis, timing closure, DFT support, and silicon bring-up using Verilog/SystemVerilog.
Lead a front-end design team focused on CPU cache subsystem micro-architecture and RTL design for Google's custom silicon, collaborating across architecture, verification, power, and physical design teams to deliver production-quality CPU subsystems.
Develops memory controller firmware for AI, ML, supercomputing, and graphics accelerators in data centers, collaborating with RTL design, DV, emulation, platform, and software teams.
New College Graduate Hardware ASIC Engineer role at NVIDIA in Shanghai, focused on SoC/chip design, verification, DFT, and post-silicon validation using VLSI, RTL, UVM, and physical design methodologies.
The FPGA Design Engineer will develop and maintain FPGA designs, core system software, and drivers for new and existing products. The role involves the full development lifecycle, including requirements analysis, RTL design, verification using VHDL, and DSP software development in C.
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping…
Role Overview The Arm Solutions Engineering Physical IP group is building a team focused on the development of custom and semi-custom digital hard macros used across Arm CPU, GPU, NPU, and SoC products. These hard…
We couldn't check your fit for this role — add a CV to your profile to see it next time.