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R&D engineer responsible for physical design and implementation of high-performance System-On-Chip ASICs (500M–800M gates) at 5nm/3nm/2nm nodes using commercial and in-house EDA tools, collaborating with RTL teams and supporting customers.
This role involves architecting and designing high-speed mixed-signal SerDes circuits and high-performance digital circuits for automotive audio-video applications. The engineer will manage the full ASIC design flow from RTL to GDSII, including verification, synthesis, and timing closure.
Lead a team to design and integrate ASIC/SOC components, focusing on power and clock management, while collaborating with cross-functional hardware and software teams.
Lead pre-silicon verification for SambaNova’s AI chips, owning methodology, testbenches, and tape-out readiness, then debug first silicon in the lab.
Designs and integrates high-performance, low-power pixel processing engines for Apple’s SoCs, writing RTL and collaborating with verification and physical design teams.
At Kandou , we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable…
Drive complex semiconductor/SoC programs from planning through silicon tape-out and post-silicon validation. Manage cross-functional teams and coordinate with vendors, foundries, and government stakeholders.
You are fascinated by microelectronics and want to push the boundaries of what is possible? Join us in developing highly integrated RF SoCs for next-generation automotive radar applications. You will shape the future…
The Senior SoC Design Verification Engineer leads the verification of complex SoC features and subsystems using SystemVerilog and UVM. The role involves driving verification methodology, ensuring silicon sign-off, and mentoring engineering teams.
The Silicon Design Staff Engineer will lead verification efforts for PCIe subsystem IP, developing testbench infrastructure and verification plans. The role requires extensive experience in ASIC design verification and proficiency in UVM and SystemVerilog to support high-performance interconnect development.
About GF GlobalFoundries (GF) is a leading manufacturer of essential semiconductors, enabling AI at scale from the cloud to the physical world. Through deep partnerships with customers, GF delivers differentiated,…
Lead multi-functional ASIC and hardware platform programs from concept to production, coordinating silicon, firmware, and system teams to deliver Cisco’s next-gen networking solutions.
NVIDIA is seeking Ph.D. students for hardware research internships focused on circuit design, ASIC/VLSI development, and electronic design automation (EDA). Interns will collaborate with research teams to develop prototypes and publish original research in areas like ML accelerators, memory design, and high-speed signaling.
NVIDIA is seeking interns for 12-week hardware ASIC design roles, focusing on tasks like RTL design, verification, and physical design. Interns will work on projects impacting AI, robotics, and accelerated computing using tools like SystemVerilog, C++, and Python.
This role is for an RTL Design Team Lead to manage a hardware team and contribute hands-on to the development of complex FPGA and ASIC IP for 5G and satellite communications. The position involves technical leadership, team mentoring, and optimizing hardware designs for performance and power efficiency.
Lead AI/ML-driven automation for ASIC design, optimizing power, performance, and area for SoCs using cutting-edge techniques like GenAI and reinforcement learning.
Develop and verify embedded firmware in C/C++ for mixed-signal power management ICs, collaborating with RTL teams to define hardware interfaces and ensure ROM-ready code.
Designs and owns RTL blocks for SambaNova’s AI-accelerating RDU ASICs, shepherding them from spec to silicon bring-up while optimizing for power, performance, and area.
Design and verify custom silicon accelerators and SoCs for Google’s AI and hardware infrastructure using SystemVerilog, UVM, and formal methods.
Integrate commercial RISC-V core soft IP with external accelerators, tailor CPU features to meet performance, power, and area requirements, modify Verilog and SystemVerilog RTL, collaborate across ASIC design…
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