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Design SoC system-level architecture, define hardware module specs with IC engineers, perform FPGA validation and silicon verification, and support customer issues.
Designs and optimizes ASIC RTL (Register Transfer Level) logic for hardware chips, ensuring functionality, performance, and manufacturability in a full-time onsite role at an engineering services company.
RTL Design Engineer responsible for CPU logic design and architecture at Intel, coding in System Verilog to develop and optimize CPU IP blocks for power, performance, and timing goals.
The Senior Digital IC Design Engineer will architect, implement, and verify MCU/DSP systems and hardware accelerators using Verilog/SystemVerilog. The role involves leading project activities, coordinating with software teams on SDK development, and improving design methodologies.
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Develops and executes pre-silicon verification strategies for ARM Cortex-M firmware controlling power management ICs, using SystemVerilog simulations to test firmware behavior, debug defects, and automate testing with Python/Perl.
FPGA Design Engineer owning the design and implementation of FPGA-based interfaces (PCIe, I2C, SPI, high-speed GT) on Xilinx UltraScale+ and Versal platforms for quantum computing control systems.
Designs and implements high-performance ASIC blocks for an AI accelerator, using SystemVerilog and industry protocols like AXI and PCIe.
Lead a team designing RTL for FPGA/ASIC signal-processing IP used in 5G base stations and satellite communications.
Senior UI/UX & Product Designer leading end-to-end design for Arabic/RTL and English/LTR web and mobile digital services, using Figma for prototyping and design systems.
Why join Upscale AI Upscale AI is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems…
Designs and verifies FPGA-based digital circuits for SoC prototyping, including RTL coding, synthesis, and HW/SW co-validation, while collaborating with cross-functional teams.
Lead digital design for power-management ICs, defining architecture, RTL, synthesis, and timing while collaborating with global teams to deliver high-efficiency converters for consumer, industrial, and automotive applications.
Designs and develops ASIC/FPGA digital systems for aerospace/defense programs, including HDL/RTL coding, simulation, timing closure, and integration. Works on advanced projects like satellite systems, aircraft platforms, and autonomous tech, with opportunities for leadership and mentorship.
Job Details: Job Description: Designs and develops FPGA circuits and IPs including FPGA core fabric logic, interconnect routing, clocking, configuration, configurable memory blocks, and network on chip.…
Design and optimize CPU microarchitectural features using SystemVerilog RTL, focusing on power, performance, and timing while collaborating with cross-functional teams.
Designs and verifies ASIC/FPGA digital hardware for aerospace/defense systems, focusing on RTL coding, architecture, and system integration under government security clearance.
Leads chip design and integration for high-speed interface innovations, owning RTL development, timing closure, synthesis, verification, and tape-out processes in a small, senior team focused on PHY-adjacent digital design.
Designs and owns ASIC power management micro-architecture for NVIDIA’s AI chips, from RTL definition to post-silicon enablement, collaborating with architecture, verification, and validation teams.
Chip Design Verification Engineer verifying and simulating performance and power management IPs using RTL verification methodologies, in close collaboration with design and architecture teams at NVIDIA.
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