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Leads PCB design for AI silicon hardware, focusing on high-complexity, high-layer-count boards (20+ layers) with ultra-high-speed interfaces (PCIe Gen5/6, CXL) and power delivery for AI accelerators. Owns layout methodology, automation, and tooling to scale hardware development.
This role involves performing IC physical design for advanced 3nm-6nm chips, managing block-level synthesis and floorplanning, and coordinating tapeout schedules. The engineer will lead complex hierarchical chip projects and collaborate with frontend and signoff teams to ensure on-time delivery.
The Standard Cell Design Engineer will design, develop, and characterize standard cell libraries for Intel's next-generation SoCs and foundry customers. The role involves circuit implementation, parasitic extraction, and developing automation flows using EDA tools and scripting languages.
This Staff Digital Design Engineer role involves leading the development of digital functions for mixed-signal products, covering the full lifecycle from architecture and RTL design to physical implementation and production maturity. The role requires expertise in SystemVerilog, digital synthesis, and DFT methodologies within a collaborative team environment.
Sr. Network Engineer designing, deploying, and supporting Gartner's global LAN/WAN enterprise environment using Cisco, Palo Alto firewalls, F5 load balancers, Infoblox DNS/DHCP, and network automation tools like Python/Terraform/Ansible.
Responsibilities Lead or contribute to component debug for customer-return and manufacturing-test failures using production ATE and electrical characterization methods. Debug and optimize ATE test programs, test…
This Staff Engineer role involves managing physical design tasks for advanced 3nm-6nm chips, including block coordination, floorplanning, and overseeing tapeout schedules. The role requires deep expertise in IC design, Linux environments, and scripting languages like Python or TCL to lead technical teams.
Customize and support Cadence ECAD applications (OrCAD, Allegro, System Capture, Pulse) at Amazon Lab126, building automations via Tcl/SKILL scripting and integrating AI/ML capabilities into hardware design workflows.
Relationship Manager - Sales REPORTS TO (SOLID & MATRIX): Position Grade: Business Unit: SME Department: Sales Sub Function: EQF Location: Number of Positions: Single / Multiple Position Type: Full Time Job Purpose…
Business Vertical: TCL Department: Business Solution Group Designation: Manager- BSG Line of Business: Central Credit Proposed Immediate Superior: Sr. Manager- BSG Grade: M4 Key Objective of the Job: To design, develop…
The Mid-Level Network Engineer will design, build, and troubleshoot complex network and security architectures for the Department of Defense. The role requires expertise in Cisco networking, routing protocols, and network security appliances while maintaining compliance with DISA STIG requirements.
Staff Digital Design Engineer responsible for FPGA/ASIC RTL design, board-level schematic capture, and system architecture for aerospace and defense applications (electronic warfare, radar, communications) using Verilog/VHDL, high-speed interfaces, and PCB tools.
Lead RTL-to-GDSII physical design implementation for next-gen high-performance processor/ASIC chips, managing teams, methodology, and tapeouts using advanced EDA tools and scripting (Tcl, Python, Perl).
Lead physical design methodology and RTL-to-GDSII implementation for next-generation high-performance processor/ASIC chips in leading-edge CMOS process technology.
Senior Staff Engineer performing physical design (place-and-route, static timing, physical verification) on next-generation high-performance processor/ASIC chips using EDA tools, with automation scripting in Shell, Python, and TCL.
Software engineer developing and maintaining clock-tree synthesis algorithms in C++ and Tcl for the Innovus place-and-route EDA tool, including debugging, testing, and optimizing performance.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Overview: This role sits at the intersection of deep protocol expertise and direct partnership with our…
Description Data Center Solutions Business Unit (DCS) delivers industry leading performance, reliability, and security in Storage Controllers, Memory Controllers, NVMe SSD Controllers, PCIe Switches and SAS Expanders…
Lead RTL/silicon design engineer for AMD's Data Accelerator team, designing custom hardware offload engines (encryption, compression, compute offloads) for SOCs powering servers, datacenters, and embedded products.
Senior engineer leading FPGA system-level design creation, lab bring-up (60% of time), and validation for Microchip's semiconductor products, using Verilog/VHDL, C, and high-speed serial protocol expertise.
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