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Note: This position is posted for Markham, but it is open to candidates across Canada, including Mississauga, Nepean, and Ottawa. The role can be hybrid or fully remote depending on your location and preference. We Are…
Job Details: Job Description: About the Role Altera is seeking a Lead Technical Program Manager to provide strategic technical program leadership for the development and delivery of next-generation FPGA products. This…
The mission of the Instrumentation Division is to develop state-of-the-art instrumentation required for experimental research programs at Brookhaven Lab and to maintain the expertise and facilities in specialized high…
Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to…
A research internship (for PhD/research MS/MTech students) at Marvell in Hyderabad focused on digital design and FPGA prototyping of next-generation protocols and system features, with a path toward translating designs into silicon. Day to day involves designing, implementing, and testing FPGA hardware in Verilog/SystemVerilog or VHDL and evaluating designs for performance, area, and timing.
Hardware Tools and Libraries InternThis role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud…
VLSI Design Verification InternshipThis role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the…
Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and…
Company Qualcomm Technologies, Inc. Job Area Engineering Group, Engineering Group > ASICS Engineering General Summary Qualcomm's validation team is a central part of the Global SoC hardware organization…
Meta is hiring an ASIC Design Verification Engineer specializing in Design for Testability (DFT) within the Infrastructure Silicon organization. We are looking for experienced engineers to develop and verify DFT…
In this position you will join a fast-paced team developing new, cutting-edge firmware for Solidigm Solid State Drives (SSD). You will utilize and grow your experience in embedded architecture, external interfaces, and…
Synchron is developing a high-channel-count neural recording ASIC in partnership with an external IC design house which owns design, simulation, test development, and fabrication. This role owns independent, in-house…
The position(s) covered by this vacancy announcement is in the Department of Defense (DoD) Acquisition Workforce Personnel Demonstration Project (AcqDemo). For more information please see: AcqDemo This position is part…
In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Network Infrastructure group is at the heart of a revolution to connectivity,…
As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and…
Lead pre-silicon IP design engineer at AMD's Strategic Silicon Solutions group, guiding a design team through SoC subsystem development integrating AMD, ARM, DSP, and NOC IP. Day-to-day spans Verilog/SystemVerilog RTL design, lint/CDC/UPF power-quality checks, and supporting verification, synthesis/STA, and post-silicon bring-up.
A senior IC engineer who architects and writes Verilog RTL for mixed-signal chips at Renesas, owns digital backend tasks like synthesis, static timing analysis, and logic equivalence checking, and mentors junior engineers. Requires 12+ years of ASIC/IC design experience with deep knowledge of the full design flow.
Principal Engineer designing wireless PHY/MAC silicon at InnoPhase IoT in San Jose: builds end-to-end simulation frameworks, DSP engines, and SystemVerilog RTL for WiFi/cellular physical layers, then drives designs through synthesis, timing closure, and verification with cross-team collaboration.
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