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This role involves architecting and designing high-speed mixed-signal SerDes circuits and high-performance digital circuits for automotive audio-video applications. The engineer will manage the full ASIC design flow from RTL to GDSII, including verification, synthesis, and timing closure.
Designs and implements digital blocks and SoC components for next-gen chiplet power delivery systems, using Verilog/SystemVerilog and collaborating with verification and physical design teams.
Principal RTL engineer owns the microarchitecture and SystemVerilog RTL for a major block of SambaNova’s AI accelerator chip, driving PPA trade-offs, timing closure, and tape-out while collaborating with architects and physical-design teams.
Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.…
Senior/Principal Physical Design Engineer at Fractile, responsible for end-to-end ASIC/SoC physical design implementation (floorplanning, placement, CTS, routing, sign-off) using EDA tools like Cadence Innovus, Synopsys Fusion Compiler, and Mentor Graphics Calibre, optimizing PPA metrics and collaborating with cross-functional teams.
Kandou is a semiconductor company pioneering high-performance interconnect and chip-to-chip communication solutions. Our engineering teams push the boundaries of what is possible in silicon design, validation, and…
At Kandou , we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems - a critical barrier to scalable…
At Kandou , we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable…
CPU Core MicroArchitect/RTL Design Engineer crafting functional units for AMD's next-generation processor cores, with a primary focus on caches and memory subsystem RTL design and coding.
The SMTS Silicon Design Engineer will develop host controller IP for high-speed I/O technologies using Verilog HDL. This role involves designing, verifying, and mentoring junior engineers to support next-generation high-performance computing and AI products.
DFX RTL design engineer on AMD's Client SOC DFX team, planning and implementing DFX features (JTAG, Scan, Boundary Scan, Debug) and low-power UPF support for next-gen microprocessors using Verilog/SystemVerilog/VHDL and scripting languages.
About Ethernovia, Inc. Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018,…
Principal Logic Design Engineer responsible for micro-architecture and RTL design of next-generation high-performance memory controllers for data centers and AI applications, using SystemVerilog/Verilog and collaborating with verification and physical design teams.
NVIDIA is seeking interns for 12-week hardware ASIC design roles, focusing on tasks like RTL design, verification, and physical design. Interns will work on projects impacting AI, robotics, and accelerated computing using tools like SystemVerilog, C++, and Python.
This role is for an RTL Design Team Lead to manage a hardware team and contribute hands-on to the development of complex FPGA and ASIC IP for 5G and satellite communications. The position involves technical leadership, team mentoring, and optimizing hardware designs for performance and power efficiency.
Principal FPGA Design Engineer at Microchip's Chandler Design Center developing and validating FPGA-based platforms for next-gen USB and Ethernet PHY products using Verilog/SystemVerilog RTL design, Vivado, and lab debug equipment.
Designs and verifies FPGA logic for Microchip PolarFire SoCs using VHDL/Verilog, integrating with RISC-V cores and Linux/RTOS drivers.
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Memwize is a VC-backed, stealth-mode startup building rack-level AI inference systems . We are seeking an experienced RTL Design Engineer to implement RTL blocks in close collaboration with architects and…
Develop and verify embedded firmware in C/C++ for mixed-signal power management ICs, collaborating with RTL teams to define hardware interfaces and ensure ROM-ready code.
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