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500 Intel Ireland Ltd.
1 views last week

SoC Logic Design Engineer

New HybridLATAMFull-time
Costa Rica

Job Details: Job Description: The Role and Impact As a SoC Logic Design Engineer, you will be responsible for creating and optimizing the Register Transfer Level (RTL) design for System-on-Chip (SoC) projects. You will…

Linux OOP Python SystemVerilog Unix +1 skills
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Silabs India Private Limited
4 views last week

Digital Design Engineer I

New On-siteNorth AmericaInternshipIntern
United States

Entry-level digital design engineer on Silicon Labs' Wireless MCU Digital Design team in Austin, TX. Day to day: designing and validating digital logic blocks for low-power wireless SoCs — RTL development, simulation and verification, debugging, and silicon bring-up. Core tech: Verilog/SystemVerilog, VLSI/digital IC design, EDA tools.

Embedded Systems Firmware IoT Rtl SystemVerilog +1 skills
79K – 146K $
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SiFive India Private Limited
2 views last week

Power Management Design Engineer

Open 7d On-siteNorth America
United States

About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive…

Confluence Git GitHub Jira Machine Learning +4 skills
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HPR
3 views last week

FPGA Design Engineer II

New On-siteNorth AmericaFull-time
United States

Designs, develops, and optimizes high-performance, ultra-low-latency FPGA compute and networking systems for electronic trading infrastructure, owning the full RTL flow from specification through synthesis and implementation, with verification support and mentoring. Uses SystemVerilog/VHDL, Linux, and tools like VCS/Verdi; full-time on-site in Needham, MA with no visa sponsorship.

C Ethernet FPGA Linux Networking +7 skills
90K – 216K $
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HPR
3 views last week

Senior Design Verification Engineer

New On-siteNorth AmericaFull-timeSenior
United States

Senior Design Verification Engineer at HPR verifies and maintains high-performance FPGA compute and networking systems used in electronic trading, owning the full verification flow — spec, test planning, SystemVerilog testbench development, simulation, and coverage closure — while mentoring junior engineers. On-site in Needham, MA.

C Ethernet FPGA Linux Networking +5 skills
112K – 280K $
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HPR
4 views last week

Senior FPGA Design Engineer

New On-siteNorth AmericaFull-timeSenior
United States

Senior FPGA Design Engineer at HPR (Hyannis Port Research) builds and optimizes ultra-low-latency FPGA compute and networking systems for electronic trading infrastructure. Owns RTL design from specification through synthesis and implementation using SystemVerilog/VHDL on Linux, mentoring junior engineers. Full-time on-site in Needham, MA.

C Ethernet FPGA Linux Networking +7 skills
112K – 280K $
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NormalComputing
14 views last week

ASIC Architect

Open 68d HybridNorth America
United States

Design custom silicon and system microarchitecture for an unconventional AI compute platform, translating transformer and diffusion workloads into energy-efficient mixed-signal compute tiles and memory hierarchies.

Accessibility AI C++ FPGA Generative AI +5 skills
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Astera Labs Early Career - North America 2027
2 views last week

AMS Design Verification Engineer Intern

North AmericaInternshipIntern
United States

Design Verification Engineer – Intern Role overview Astera Labs is seeking a motivated Digital Design Verification Intern to join our San Jose design team. This internship offers hands-on experience in functional…

AI Asic Automation Bash Cloud +13 skills
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Astera Labs Early Career - North America 2027
1 views last week

AMS Digital Design Engineer NCG

North America
United States

Digital RTL Design Engineer – NCG Role overview Astera Labs is seeking a motivated Digital RTL Design Engineer to join our San Jose design team. This is an opportunity for a new college graduate to build ownership in…

AI Asic Bash Cloud Ethernet +10 skills
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Astera Labs Early Career - North America 2027
2 views last week

AMS Digital Design Engineer Intern

North AmericaInternshipIntern
United States

Digital RTL Design Engineer – Intern Role overview Astera Labs is seeking a motivated Digital RTL Design Intern to join our San Jose design team. This internship offers hands-on experience in digital logic design and…

AI Asic Bash Cloud Ethernet +10 skills
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Astera Labs
11 views last week

Senior Design Verification Engineer

Open 25d North AmericaSenior H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Astera Labs is hiring a Senior Design Verification Engineer in San Jose to verify next-generation connectivity silicon (PCIe Gen 6/7, UALink, UCI) for rack-scale AI infrastructure. Day to day: building UVM/SystemVerilog testbenches, defining coverage models, debugging simulations, and driving coverage closure with RTL and post-silicon teams.

AI Automation Ethernet Firmware PCIe +6 skills
149K – 165K $
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Astera Labs
7 views last week

Tech Lead Engineer, Design Verification

Open 25d North AmericaLead H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Lead design verification for Astera Labs' next-generation connectivity silicon (PCIe Gen6/7, UALink, UCIe) that powers rack-scale AI infrastructure. Day to day: build UVM/SystemVerilog testbenches, define verification plans and coverage models, debug simulations, drive regression automation, and partner with RTL, firmware, and post-silicon teams through coverage closure and silicon bring-up.

AI Automation Ethernet Firmware Observability +7 skills
176K – 195K $
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Astera Labs
7 views last week

Principal Logic Design Engineer - UALink IP/Subsystem

Open 37d APACPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
India

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…

AI Ethernet Firmware Networking PCIe +2 skills
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Astera Labs
6 views last week

Principal Logic Design Engineer

Open 24d APACPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
India

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…

AI Ethernet PCIe Root Cause Analysis Rtl +2 skills
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Astera Labs
6 views last week

Design Verification Tech Lead- SerDes/PHY IP

Open 32d North AmericaLead H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Principal-level design verification tech lead owning functional verification of high-speed SerDes/PHY IP for AI infrastructure connectivity. Day to day: architecting UVM testbenches, driving coverage closure to tape-out, verifying against PCIe Gen 6/7, UALink, UCIe, and Ethernet PHY specs, and mentoring DV engineers. Core stack: SystemVerilog/UVM, analog/mixed-signal co-simulation, Real Number Mod

AI Automation Ethernet Firmware PCIe +5 skills
160K – 200K $
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Astera Labs
17 views last week

Senior Digital Design Engineer

Open 43d North AmericaSenior H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Canada

A Senior Digital Design Engineer at Astera Labs designs high-performance connectivity silicon for AI infrastructure, owning micro-architecture, RTL implementation, synthesis, timing closure, and IP integration for PCIe/Ethernet controllers, bridges, switches, and SerDes interfaces. Core tech includes SystemVerilog/Verilog, Synopsys and Cadence tools, and Python/Perl automation.

AI Automation CAD CI/CD Embedded Software +11 skills
140K – 155K CAD
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Astera Labs
9 views last week

Senior Design Verification Engineer

Open 42d North AmericaSenior H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Canada

Builds and maintains UVM-based verification environments (SystemVerilog with C/C++ via DPI/PLI) for connectivity silicon used in rack-scale AI infrastructure, writing tests, assertions, and coverage while debugging across simulation, co-simulation, and FPGA emulation alongside RTL designers.

AI C++ Ethernet FPGA InfiniBand +6 skills
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Astera Labs Early Career - North America 2027
1 views last week

Design Architecture Engineer Intern

North AmericaInternshipIntern
United States

Design Architecture Engineer Intern About the role Astera Labs is seeking a Design Architecture Engineer Intern to help define complex ASIC and system designs from product requirements through implementation. You will…

Acceptance Criteria C++ Embedded Systems Ethernet Firmware +7 skills
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Astera Labs Early Career - North America 2027
2 views last week

Digital Design Engineering Intern

North AmericaInternshipIntern
United States

Digital Design Intern About the role Astera Labs is seeking a Digital Design Intern to contribute to the development of ASIC and digital hardware blocks. You will gain hands-on experience with RTL implementation,…

Asic C++ Embedded Systems Firmware FPGA +7 skills
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Astera Labs Early Career - North America 2027
3 views last week

Digital Design Engineer Intern (Toronto)

North AmericaInternshipIntern
Canada

Digital Design Intern (Toronto) Location: Toronto, Ontario, Canada Employment type: Internship About Astera Labs Astera Labs develops purpose-built connectivity solutions for rack-scale AI infrastructure. Our…

AI Asic Bash Cloud C++ +9 skills
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