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An ASIC digital engineer specializing in FPGA prototyping, emulation, and system-level debugging to support platform bring-up, hardware/software co-verification, and end-user collaboration.
Senior Staff VLSI Design Engineer coding C++ and SystemC functional models and testbenches for memory/storage products, validating models using SystemC/SV/UVM, debugging firmware issues, and mentoring junior engineers.
Lead VLSI design verification for complex IP blocks and SoC designs using UVM, SystemVerilog, and formal verification tools like Xcellium, Verdi, and JasperGold.
General Dynamics Electric Boat is seeking hardware and software engineers to develop and integrate electric drive propulsion control systems for U.S. Navy submarines. The role involves embedded software development, hardware design, and rapid prototyping using languages like C, C++, and Python.
General Dynamics Electric Boat is hiring systems, hardware/software, and project engineers to develop electric drive control systems for U.S. Navy submarines. The roles involve model-based design, embedded software development, and project management using tools like MATLAB, Simulink, and IBM Rational DOORS.
Principal Digital Design Engineer owning the architecture and RTL development of a configurable IO subsystem for onsemi's microcontroller platform, using SystemVerilog, Python-based design generators, and UVM verification in Allen, TX.
The Chip Software Engineer will design and build software tooling, firmware, and infrastructure to support semiconductor design, verification, and post-silicon validation. The role requires strong proficiency in C, C++, and Python to work alongside hardware teams in accelerating silicon development cycles.
The Embedded Semiconductor Engineer will design and build software tooling, firmware, and infrastructure to support semiconductor design, verification, and post-silicon validation. The role involves working with C, C++, and Python to optimize silicon development cycles and compute-intensive workflows.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This is an opportunity to join a dynamic team of experienced engineers developing physical IP for…
DSP Hardware Design Engineer at Cadence responsible for CPU/DSP/NPU hardware accelerator design and tape-outs using Verilog/SystemVerilog, EDA tools, and Perl scripting.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position Overview As a Senior Principal Design Engineer, you will be responsible for the design,…
Job Description: 1. Responsible for micro-architecture design and RTL implementation of high-performance CPU front-end pipeline, including instruction fetch, branch prediction, instruction decode, dispatch and…
The GPU Digital Frontend Design Engineer will define microarchitecture, design RTL for high-performance GPU/AI accelerator chips, and optimize for power, performance, and area. The role involves collaborating with verification, software, and physical design teams using Verilog/SystemVerilog and standard EDA tools.
The SoC Digital Design Engineer will design and implement hardware accelerators for video codecs and SoC subsystems using Verilog/SystemVerilog. The role involves architecture definition, RTL implementation, and cross-functional collaboration to optimize power, performance, and area for large-scale video platforms.
This entry-level role involves developing and verifying digital ICs and SoCs for aerospace and defense applications. Engineers will work on FPGA/ASIC design, simulation, and hardware integration using industry-standard tools and HDL languages.
Job Details: Job Description: Altera is seeking a technically strong Transceivers & Protocol IP Application Engineer to be based in San Jose California Altera Office to help customers and partners successfully…
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Profile Role Title Lead Design Engineer, SoC / Subsystem / IP Design Experience 4to 18 years…
Design Verification Engineer responsible for developing verification plans, test benches, and running regressions to ensure first-pass silicon success for analog and mixed-signal ICs at Texas Instruments in Dallas.
Designs and leads high-speed analog transceiver circuits for silicon photonics and wireline systems, collaborating with cross-functional teams to drive specifications and validate performance in next-gen AI data center infrastructure.
Senior staff engineer verifying AI data-center photonics chips using UVM, AMS, and emulation to ensure designs meet performance and functional goals.
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