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GLOBALFOUNDRIES US Inc.
3 views last week

Foundation IP Design Verification Intern (Summer 2027)

New On-siteNorth AmericaInternshipIntern H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Summer 2027 internship at GlobalFoundries supporting design verification of Foundation IP — standard-cell libraries, memories, block-level IP, and chip-level integration. Day-to-day work spans SPICE and Verilog simulation, formal verification, post-silicon analysis and silicon debug, plus scripting/CAD automation and AI-assisted performance prediction.

AI Automation Bash CAD Cloud +4 skills
20 – 40 $ / hr
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NormalComputing
13 views last week

Hardware Engineer, Physical Design

Open 84d HybridNorth America
United States

Hardware Engineer specializing in RTL/PD, optimizing designs from microarchitecture to tapeout for AI-native ASICs at Normal Computing, a deep-tech semiconductor startup.

Accessibility AI Asic HPC Python +2 skills
100K – 200K $ / mo
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Astera Labs Early Career - North America 2027
2 views last week

AMS Design Verification Engineer Intern

New North AmericaInternshipIntern
United States

Design Verification Engineer – Intern Role overview Astera Labs is seeking a motivated Digital Design Verification Intern to join our San Jose design team. This internship offers hands-on experience in functional…

AI Asic Automation Bash Cloud +13 skills
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Astera Labs
4 views last week

Principal Physical Design CAD Engineer

New MENAPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel

Astera Labs is hiring a Principal Physical Design CAD Engineer for its new Israel R&D center to build and automate physical design CAD flows (synthesis through P&R, timing, power, signoff) for AI connectivity chips, using Synopsys Fusion Compiler plus Tcl/Python automation and exploring GenAI-based methodologies.

Agentic AI AI Automation CAD CI/CD +9 skills
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Astera Labs Early Career - North America 2027
1 views last week

AMS Digital Design Engineer NCG

New North America
United States

Digital RTL Design Engineer – NCG Role overview Astera Labs is seeking a motivated Digital RTL Design Engineer to join our San Jose design team. This is an opportunity for a new college graduate to build ownership in…

AI Asic Bash Cloud Ethernet +10 skills
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Astera Labs Early Career - North America 2027
2 views last week

AMS Digital Design Engineer Intern

New North AmericaInternshipIntern
United States

Digital RTL Design Engineer – Intern Role overview Astera Labs is seeking a motivated Digital RTL Design Intern to join our San Jose design team. This internship offers hands-on experience in digital logic design and…

AI Asic Bash Cloud Ethernet +10 skills
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Astera Labs
4 views last week

Teach Lead Physical Design Engineer

New APACLead H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Singapore

Lead physical design engineer at Astera Labs in Singapore implementing next-generation high-speed transceiver IPs at TSMC 3nm and advanced nodes. Day-to-day covers floorplanning, placement, CTS, routing, EM/IR and signoff (DRC/LVS/ERC) using ICC2, Innovus, Voltus, RedHawk, and Calibre, plus Tcl/Python/Perl flow automation.

AI Automation Ethernet PCIe Perl +3 skills
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Astera Labs
4 views last week

Principal Physical Design Engineer

New APACPrincipal H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Singapore

Physical design engineer at Astera Labs implementing next-generation high-speed transceiver IPs at TSMC 3nm and advanced nodes: floorplanning, placement, CTS, routing, EM/IR and congestion analysis, ECOs, and DRC/LVS/ERC signoff using ICC2, Innovus, Voltus, RedHawk, and Calibre, plus Tcl/Python/Perl flow automation.

AI Automation Ethernet PCIe Perl +3 skills
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Astera Labs
11 views last week

Senior Design Verification Engineer

Open 25d North AmericaSenior H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Astera Labs is hiring a Senior Design Verification Engineer in San Jose to verify next-generation connectivity silicon (PCIe Gen 6/7, UALink, UCI) for rack-scale AI infrastructure. Day to day: building UVM/SystemVerilog testbenches, defining coverage models, debugging simulations, and driving coverage closure with RTL and post-silicon teams.

AI Automation Ethernet Firmware PCIe +6 skills
149K – 165K $
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Astera Labs
7 views last week

Tech Lead Engineer, Design Verification

Open 25d North AmericaLead H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Lead design verification for Astera Labs' next-generation connectivity silicon (PCIe Gen6/7, UALink, UCIe) that powers rack-scale AI infrastructure. Day to day: build UVM/SystemVerilog testbenches, define verification plans and coverage models, debug simulations, drive regression automation, and partner with RTL, firmware, and post-silicon teams through coverage closure and silicon bring-up.

AI Automation Ethernet Firmware Observability +7 skills
176K – 195K $
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Astera Labs Early Career - North America 2027
3 views last week

Physical Design Engineer Intern (Toronto)

New North AmericaInternshipIntern
Canada

Physical Design Engineer Intern (Toronto) Location: Toronto, Ontario, Canada Employment type: Internship About Astera Labs Astera Labs develops purpose-built connectivity solutions for rack-scale AI infrastructure. Our…

AI Asic Automation Bash CAD +8 skills
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Astera Labs Early Career - North America 2027
3 views last week

Digital Design Engineer Intern (Toronto)

New North AmericaInternshipIntern
Canada

Digital Design Intern (Toronto) Location: Toronto, Ontario, Canada Employment type: Internship About Astera Labs Astera Labs develops purpose-built connectivity solutions for rack-scale AI infrastructure. Our…

AI Asic Bash Cloud C++ +9 skills
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Astera Labs Early Career - North America 2027
last week

Design Verification Engineer Intern (Toronto)

New North AmericaInternshipIntern
Canada

Design Verification Engineer Intern (Toronto) Location: Toronto, Ontario, Canada Employment type: Internship About Astera Labs Astera Labs develops purpose-built connectivity solutions for rack-scale AI infrastructure.…

AI Bash Cloud C++ Git +8 skills
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Astera Labs Early Career - North America 2027
2 views last week

Physical Design Engineer Intern (DM)

New North AmericaInternshipIntern
United States

Physical Design Engineer Intern (DM) Astera Labs · San Jose, CA · Internship · On-site About Astera Labs Astera Labs builds connectivity solutions that help power modern AI infrastructure. Our silicon teams develop…

AI Asic Bash Bitbucket CAD +9 skills
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Astera Labs Early Career - North America 2027
1 views last week

Physical Design Engineer Intern

New North AmericaInternshipIntern
United States

Physical Design Engineer Intern Astera Labs · San Jose, CA · Internship · On-site About Astera Labs Astera Labs builds connectivity solutions that help power modern AI infrastructure. Our silicon teams develop complex…

AI Asic Bash Bitbucket CAD +9 skills
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Astera Labs
6 views last week

Senior Physical Design Engineer

Open 80d APACSenior H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Singapore

Leads physical design for next-gen transceiver IPs on TSMC 3nm nodes, handling floorplanning, placement, CTS, routing, and verification to ensure timing/power/area convergence with RTL and STA teams.

AI Automation Ethernet PCIe Perl +3 skills
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Astera Labs
6 views last week

Applications Engineering Manager - Ethernet

Open 134d North America H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
United States

Principal Product Applications Engineer at Astera Labs designs and troubleshoots high-speed Ethernet connectivity for AI infrastructure, working directly with customers to deploy Taurus Smart Cable Modules in data centers.

AI Automation Ethernet GPU Machine Learning +9 skills
158K – 230K $
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Qorvo
14 views last week

RF/Analog IC Design Intern

Open 51d InternshipIntern H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.

Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve…

Bash CAD Cadence Virtuoso Fea IoT +3 skills
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Qorvo
10 views last week

Design Engineering Intern

Open 51d InternshipIntern H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.

Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve…

Bash CAD Cadence Virtuoso Fea IoT +3 skills
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Qorvo
9 views last week

Senior Analog/RF IC Design Engineer

Open 51d Senior H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.

Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve…

IoT MATLAB Python Tcl Verilog +1 skills
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