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Design Verification Engineer builds and runs testbenches for FPGA/ASIC hardware used in low-latency trading systems, using SystemVerilog, UVM, and open-source tools like Verilator and Cocotb.
Design and optimize high-performance ASICs and FPGAs for low-latency trading systems, using industry-standard physical design tools and scripting to close timing and improve PPA.
Manage complex ASIC/silicon projects end-to-end — planning, cross-functional coordination across architecture/RTL/DV/physical design/manufacturing, vendor and IP partner management, and risk mitigation — using standard project-management tools.
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…
Job Summary: We are seeking an experienced Senior Principal Engineer - Digital Design to lead the micro-architecture, design, and execution of next-generation UA Link Switch solutions within the Memory Interface…
Senior project lead of a team of engineers in the tasks of guaranteeing specification compliance of analog & mixed signal design by means of advanced verification methodologies and concepts. It involves definition,…
Role Overview We are seeking an experienced Applications Engineer specializing in advanced high-speed Ethernet SerDes technologies. In this key technical role, you will bridge the gap between silicon architecture,…
An engineer who builds and runs the development infrastructure and AI services behind AMD's AI-assisted silicon design program — modernizing source control, CI/CD, and compute/storage platforms, plus telemetry and benchmarking to measure AI impact. Core stack spans Python, Git/GitHub, CI/CD, LLM ops, and EDA compute (LSF/Slurm, Linux) alongside ASIC design workflows.
Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a…
Meet the Team Common Hardware Group (CHG) Power is a central team that supports power design across various products like Cisco 8000 Series Routers, Catalyst 9000 switches, IoT, and many others. As part of the central…
RELOCATION ASSISTANCE: No relocation assistance available CLEARANCE REQUIRED FOR START: No CLEARANCE TYPE: Top Secret TRAVEL: Yes, 10% of the Time Description At Northrop Grumman, our employees have incredible…
Company: Qualcomm Korea YH Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable…
Job Title/Code: Senior Electrical Engineer Department: Engineering Reports To: Engineering Manager Job Type: Full Time, Exempt Location: Concord, CA (On-Site) At EMCORE LLC, we're committed to attracting and…
Designs next-generation ASICs and FPGAs for SpaceX's Starlink satellite and ground network, taking chips from architecture through RTL design in SystemVerilog/Verilog, optimization, implementation, and lab bring-up/validation. Core skills: RTL design, SoC integration, EDA tools, and scripting with Python/C++.
Designs SoC-level RTL for Google's TPU AI accelerators, focusing on clock control subsystems, chassis infrastructure, and low-power techniques using SystemVerilog. Works cross-functionally with architecture, power, design validation, and physical design teams to take custom silicon from concept to production.
Quantum Motion is a fast-growing quantum computing start-up based in London founded by internationally renowned researchers from UCL and Oxford University with over 40 years’ experience in developing qubits and quantum…
About Rivian Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract. As a company, we…
1. 致力打造世界一流的深度学习硬件计算平台， 跟踪深度学习及系统硬件架构的发展，设计开发高性能低功耗的架构、芯片及硬件产品。 2. 针对阿里巴巴集团业务发展需求，与阿里巴巴的算法和业务团队和作， 规划设计与业务相匹配的异构计算软硬件产品构架。 3. 确保前端设计的质量检查，以及跟后端流程的协作。 1. Build the world-class deep learning platforms. Follow closely…
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