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Lead a team designing custom hardware accelerators for servers and data centers using RTL, ASIC flows, and scripting tools.
Build and run on-premise Kubernetes clusters and infrastructure for AI training/inference, automating CI/CD, storage, and networking to accelerate model development at scale.
Team Credo is looking for a Principal Design Engineer to join our mission to transform connectivity at scale. In this role, you will be responsible for the RTL architecture, design, implementation, and verification of…
Designs and architects System-on-Chip IP blocks, defining roadmaps and guiding cross-functional teams through development, verification, and validation for next-gen ASICs.
Designs high-voltage analog and mixed-signal ASICs for automotive applications, leading architecture, verification, and safety-critical trade-offs in BCD technologies.
Designs high-speed SoC networking engines and interconnect fabrics for custom AI servers, optimizing distributed AI workloads with RDMA, RoCEv2, and collective-operation acceleration.
Design and implement digital and mixed-signal chips for power management and automotive systems using ASIC tools, synthesis, and verification.
Design and develop ASIC hardware for Axis’s ARTPEC SoC chips, focusing on digital logic, HDLs (SystemVerilog), and EDA tools to power surveillance cameras.
Develop and validate custom camera ASICs for Ring smart home devices, leading on-site chip bring-up and board-level integration across EVT/DVT/PVT phases.
Design and deliver low-power SoCs for Ring and Blink devices, owning physical implementation, timing closure, and silicon bring-up to meet PPA targets.
Owns design-for-test (DFT) strategy for complex ASIC/SoC chips, implementing scan, ATPG, and test compression to maximize fault coverage and silicon yield.
Designs and implements RTL code and micro-architectures for digital IPs and SoCs in the automotive domain, following the full ASIC flow.
We Are At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,…
Lead the design of next-gen ASIC IP for AI-driven data movement, collaborating across teams to deliver high-performance, secure, and power-efficient silicon solutions for AMD’s server, data center, and embedded products.
Design Verification Engineer builds and verifies RTL components in Verilog/SystemVerilog to improve AI model training and evaluation workflows, using UVM and LLM-based tools.
Designs and codes RTL for custom silicon subsystems using Verilog/VHDL, integrates IP, and runs simulations and checks to deliver high-performance hardware for Google’s products.
Design and develop embedded firmware for Xilinx FPGAs and PIC microcontrollers using VHDL and C/C++, integrating hardware into bespoke systems.
Designs and executes SoC verification for AMD’s next-gen ASIC and FPGA chips, writing testbenches in SystemVerilog/UVM and debugging failures to ensure bug-free silicon.
Design verification engineer building PCIe interconnect IP testbenches using UVM/SystemVerilog to validate high-performance ASIC features for AMD’s GPUs, APUs, servers, and consoles.
Design verification engineer at AMD, building and automating tests for next-gen network processors and SmartNICs using UVM, SystemVerilog, and AI-assisted workflows.
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