Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Design and integrate RTL for mixed-signal power management IP, drive timing closure, and tape-out while collaborating with analog, firmware, and physical design teams.
ASIC Design Verification Engineer responsible for owning verification strategy, coverage closure, and system-level testing for AMD’s mixed-signal power management IP, including RTL design and collaboration with analog/firmware teams.
Develops and maintains emulation infrastructure for Google Cloud’s TPU hardware, focusing on verifying complex digital designs and debugging emulation platforms to accelerate AI/ML hardware acceleration.
Leads verification of complex SoC subsystems (e.g., memory/cache, coherency, PCIe/DDR) using UVM/SystemVerilog, ensuring functionality, performance, and security. Owns test strategy, debugging, and cross-team collaboration for sign-off.
Designs and owns RTL blocks for SambaNova’s AI-accelerating RDU ASICs, shepherding them from spec to silicon bring-up while optimizing for power, performance, and area.
Builds and maintains hardware emulation models for SambaNova’s AI workload accelerator (RDU), enabling pre-silicon software bring-up, performance verification, and verification acceleration. Works with RTL teams to ensure emulation-readiness, owns platform automation, and advises cross-functional teams on emulation strategy.
Configure and integrate RISC processor IP into SoC platforms, customize processor features, develop RTL wrappers and system glue logic, integrate interconnects and interrupt controllers, support verification and system…
Lead physical design (RTL-to-GDS) for AMD’s next-gen AI and high-performance ASICs, driving PnR, timing closure, and tape-outs while collaborating with architects and EDA vendors.
Designs and implements RTL for SoC PAD/PFC logic (pin multiplexing, I/O control) using Verilog/SystemVerilog, in-house tools, and automation scripts to ensure design quality and integration.
Director of Physical Design Location: Austin, Texas, United States Department: Physical Design Company Overview Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the…
Lead a team to architect and execute advanced verification strategies for next-gen semiconductor products using SystemVerilog, UVM, and emulation platforms.
Senior Design Verification Engineer at HPE focused on emulation-based verification of complex digital designs, building UVM/SystemVerilog testbenches and running designs on platforms like Palladium, ZeBu, and Veloce.
Digital Design Engineer on a 12-month contract managing IP/RTL design and verification for a global semiconductor company, using VHDL/Verilog, scripting languages, and communication IPs.
The Application Engineer provides technical support and guidance to customers for Altera (Intel) FPGA-based solutions, including RTL design, custom IP development, and system-level optimization. The role involves collaborating with field teams and suppliers to solve complex design challenges and develop reference designs.
Lead RTL development of AI-enabled RISC-V CPU cores and matrix engines at a semiconductor foundry, covering microarchitecture, vector/matrix datapath design, and verification using SystemVerilog/Verilog.
About X X Corporation (Nasdaq: X), a market leader in MEMS timing, offers MEMS-based silicon timing system solutions. X configurable solutions offer a rich feature set that enables customers to differentiate their…
Lead ASIC RTL Design Engineer — Remote (U.S.) - No visa sponsorship Role Summary Our client, a leader in AI Compute is seeking a senior-level ASIC design engineer to drive the development of high-performance silicon…
DFT (Design for Testability) Engineer Role Summary: We are seeking a DFT Engineer to design and implement testability structures for complex ASIC/SoC designs, ensuring high test coverage, manufacturing yield, and…
We are hiring an experienced digital designer to work on the next generation NVM (non-volatile memory) controller for analog compute-in memory technology. The candidate will be responsible for the design, development,…
Do you love crafting elegant solutions to the hardest problems in audio and acoustics? Are you a big-picture, forward-thinking engineer who understands how audio subsystems integrate into a SoC and a system? At Apple,…
We couldn't check your fit for this role — add a CV to your profile to see it next time.
