Tech jobs

Astera Labs

Open 44d APACLead H-1B sponsor history Canada LMIA employer

Lead Logic Design Engineer

India

Lead Logic Design Engineer leading RTL and microarchitecture development for UALink-based IP/subsystems at a semiconductor company building AI infrastructure connectivity. Day to day: designing high-performance control/data-path logic in SystemVerilog, optimizing performance/power/latency, and collaborating with verification, SoC, and physical design teams.

AI Ethernet PCIe SystemVerilog Verilog

Astera Labs

Open 37d APACLead H-1B sponsor history Canada LMIA employer

Lead Logic Design Engineer

India

A senior hands-on role leading microarchitecture and RTL development for complex connectivity IPs/subsystems (PCIe, CXL, Ethernet, UALink, UCIe) at Astera Labs in Bengaluru, owning designs from spec through integration and post-silicon debug. Core technologies: SystemVerilog/Verilog, high-speed data paths, flow control, simulation, CDC, synthesis, and timing.

AI Ethernet PCIe Root Cause Analysis Rtl +2 skills

Astera Labs Early Career - North America 2027

North AmericaInternshipIntern

Design Verification Engineer Intern

AI Bash Confluence Corrective Action C++ +12 skills

Design Verification Engineer Intern Astera Labs · San Jose, CA · Internship · On-site About Astera Labs Astera Labs builds connectivity solutions that help power modern AI infrastructure. Our Hardware Engineering teams…

Astera Labs

Open 53d North AmericaPrincipal H-1B sponsor history Canada LMIA employer

Principal Design Verification Engineer- SerDes/PHY IP

AI Automation Ethernet Firmware PCIe +5 skills

Astera Labs is hiring a Principal Design Verification Engineer to own functional verification of high-speed SerDes/PHY IP for its AI connectivity semiconductors. Day to day, this person architects UVM/SystemVerilog verification environments, drives coverage closure through tape-out, and verifies PHY behavior against PCIe Gen 6/7, UALink, UCIe, and Ethernet standards, including analog/mixed-signal

207K – 230K $

AMD

AI Analytics API Asic Automation +17 skills

AI Platform Engineer, Silicon Design Infrastructure

North America

Canada

AMD is hiring a hands-on platform engineer to build and run the developer infrastructure and AI tooling behind its AI-assisted silicon design program — modernizing source control, CI/CD, compute/storage, plus telemetry and benchmarking for AI solutions. Core stack includes Python, Git/GitHub, Linux, Slurm/LSF, and LLM operations.

Inversion

Open 129d North AmericaFull-timeSenior

Senior Embedded Software Engineer (Avionics)

Automation Ccpa CI/CD C++ Embedded Software +19 skills

Develops and maintains safety-critical embedded flight software in C/C++ for spacecraft avionics, integrating with microcontrollers and real-time systems to support hypersonic reentry operations.

139K – 201K $

Qorvo

Open 52d Principal H-1B sponsor history

Senior Principal Analog/RF Design Engineer (m/f/d)

Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve…

Cadence Virtuoso Cmos IoT SystemVerilog

Skyworks Solutions

Agentic AI AI Automation Cadence Virtuoso Embeddings +11 skills

Sr. Design Automation Engineer

Open 52d Senior

Description We are building an intelligent analog and mixed-signal design automation flow that applies agentic AI and machine learning to modernize design and verification practice. You will join a central engineering…

Skyworks Solutions

A/B Testing Agentic AI AI Anomaly Detection API +19 skills

Sr. Design Automation Engineer

Open 52d Senior

Description We are building an intelligent analog and mixed-signal design automation flow that applies agentic AI and machine learning to modernize design and verification practice. You will join a central engineering…

Murata Manufacturing

Automation Embedded Systems Firmware LabVIEW MATLAB +7 skills

Senior Mixed-Signal PMIC Design Engineer

Open 52d HybridSenior

Eta Wireless is solving the fundamental problem of RF power amplifier power consumption in communications devices. We pioneered Digital Envelope Tracking (DET) technology and have since been acquired by Murata…

TSMC

C++ Python SystemVerilog Tcl Uvm +1 skills

Design Verification Engineer

Open 52d

Job Description • Verify TSMC’s product like ARM processor based SOC and memory subsystem test chips • Develop verification methodology and implement test bench components using System Verilog, UVM, and low power…

ams OSRAM

Open 52d North AmericaStaff

Senior Staff Digital Design Engineer

Agile Bash Cadence Virtuoso Perl Python +6 skills

Senior digital IC design engineer at ams OSRAM's Plano, TX site who designs, verifies, synthesizes, and brings up silicon for sensor/imaging mixed-signal semiconductors. Core stack: Verilog/SystemVerilog, UVM, low-power and CDC/LEC flows, and Cadence tools like Xcelium, Genus, SpyGlass, and JasperGold.

QualityAI

AI Cloud Networking SystemVerilog Uvm +1 skills

Senior CPU Design Verification Engineer

Open 43d UKSenior

United Kingdom

Senior engineer on an AI/silicon R&D team verifying custom CPU and digital ASIC designs: building constrained-random SystemVerilog/UVM verification environments (or formal SVA), writing coverage, debugging with design engineers, and driving coverage closure through tape-out.

Capgemini

Automation FPGA SystemVerilog Uvm Verilog

Design Verification Engineer

Open 40d Europe

Greece

An onsite Design Verification Engineer role in Thessaloniki, Greece, building UVM-based verification environments in SystemVerilog to validate high-performance digital IP and SoC designs, with a focus on DDR memory controller/PHY interfaces, regressions, and coverage closure.

Capgemini

AI Cloud Ethernet Generative AI PCIe +5 skills

Senior Design Verification Engineer

Open 40d EuropeSenior

Ukraine

Senior Design Verification Engineer on Capgemini Engineering's expanding Ukraine VLSI team: owns IP/SoC verification from RTL through emulation, defines and improves DV methodology, and builds UVM-based testbenches. Core stack is SystemVerilog, UVM/OVM, protocol knowledge (AHB/AXI, PCIe, USB, DDR) and Perl/TCL/Python scripting.

MIT Lincoln Laboratory

Open 36d North AmericaStaff

Technical Staff - Embedded Systems Architect

Assembly Automation Bash C++ Embedded Systems +14 skills

Design, develop, and field embedded systems for national-security space applications in MIT Lincoln Laboratory's Electronics for Contested Space Group — FPGA firmware (VHDL/Verilog), digital interfaces like SPI/PCIe, DSP, and hardware/software integration, with lab and field testing. Requires an EE/CE graduate degree plus 8 years (or BS + 10) and U.S. citizenship; Top Secret clearance desired.

145K – 220K $

MIT Lincoln Laboratory

Open 36d North AmericaStaff

Associate Staff - Embedded Systems Engineer

Assembly Automation Bash C++ Embedded Systems +14 skills

MIT Lincoln Laboratory's Electronics for Contested Space Group in Lexington, MA is hiring an embedded systems engineer to design, develop, test, and field embedded hardware and FPGA firmware supporting national security space systems. Day-to-day work centers on HDL development (VHDL/Verilog/SystemVerilog), FPGA implementation and debug, hardware/software integration, and lab testing with equipment

116K – 182K $

QualityAI

Senior CPU Design Verification Engineer

Open 24d EuropeSenior

Romania

Senior engineer on an R&D team verifying custom silicon (CPU/ASIC) designs for consumer products: builds constrained-random verification environments with SystemVerilog/UVM, uses SVA and formal tools, writes coverage, debugs with design engineers, and drives verification closure through tape-out. Based in Bucharest, Romania.

SystemVerilog Uvm

Qorvo

Open 22d North AmericaPrincipal H-1B sponsor history

Principal Digital IC Design Engineer

Asic Automation Bash CAD IoT +6 skills

Qorvo is hiring a Principal Digital IC Design Engineer in Richardson, TX to lead full-flow ASIC development — from architecture and RTL (SystemVerilog) through synthesis, place & route, STA, physical verification, and silicon bring-up — using Synopsys/Cadence EDA toolchains and Python/TCL scripting.