Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Senior Staff Design Verification Engineer at Lightmatter verifies advanced AI data center photonics and digital/analog designs using UVM, AMS, and emulation, collaborating with cross-functional teams to ensure high-quality chip tapeouts.
Northwood is a modern space infrastructure company bringing the benefits of space to the masses through advanced communications technology. We are building a global network of phased array ground stations that enable…
This role involves developing and scaling an AI-assisted silicon design framework using agentic ecosystems, RAG, and LLM orchestration. The engineer will build production-ready AI workflows to automate and optimize the silicon IP development lifecycle.
Junior engineer builds and runs test environments to verify next-gen AI connectivity chips using SystemVerilog/UVM and debugs hardware issues with design teams.
Principal Design Verification Engineer at Astera Labs designs and verifies advanced ASICs for AI infrastructure using SystemVerilog, UVM, and scripting languages, ensuring robust connectivity solutions for server and networking applications.
Designs high-performance digital blocks for AI infrastructure chips, using Verilog/SystemVerilog and EDA tools to solve data bottlenecks in semiconductor connectivity solutions.
Senior engineer builds and runs test environments to verify high-performance AI connectivity chips using SystemVerilog/UVM, ensuring flawless silicon for next-gen data centers.
Designs and implements verification environments for high-performance semiconductor chips in AI infrastructure, using SystemVerilog/UVM to validate digital blocks and subsystems.
Designs and implements digital blocks for semiconductor chips powering AI infrastructure, using Verilog/SystemVerilog and RTL coding principles with industry EDA tools.
Leads timing closure and sign-off for high-speed connectivity ASICs at Astera Labs, using advanced STA tools and methodologies for 7nm+ SoCs in AI infrastructure.
The Lead IP/SoC Design Verification Engineer will plan and execute verification strategies for AMD's Soft IP cores using UVM, SystemVerilog, and formal verification techniques. The role involves driving verification closure, maintaining CI/CD regression infrastructure, and collaborating with cross-functional teams to ensure high-quality silicon-proven IP.
Role Overview We are seeking a highly experienced Staff Verification Engineer to lead the design verification of next-generation high-speed interconnect IPs and SoCs. The ideal candidate will bring deep expertise in…
Senior FPGA engineer designs and deploys low-latency quantum control systems, integrating FPGA hardware with customer setups and troubleshooting quantum experiments.
Ingeteam , empresa líder especializada en ingeniería eléctrica y en el desarrollo de equipos eléctricos, motores, generadores y convertidores de frecuencia busca incorporar un/a Ingeniero/a de Diseño FPGA para…
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
Designs and verifies next-gen ASIC/FPGA SoCs using SystemVerilog/UVM, ensuring bug-free silicon by collaborating across global teams.
Lead an FPGA & DSP engineering team in Sydney, developing RF detection and defeat products using software-defined radios, FPGAs, ARM-based embedded systems, and signal processing for electronic warfare applications.
THE ROLE: You will plan, develop, and execute the SoC verification of new and existing features for AMD’s ASIC and FPGA SoCs, ensuring there are no bugs in the final design. THE PERSON: You have a passion for…
Come join Analog Devices (ADI) – a place where Innovation meets Impact. For more than 55 years, Analog Devices has been inventing new breakthrough technologies that transform lives. At ADI you will work alongside the…
Develops firmware and FPGA logic for high-precision motion control systems, writing C++ for DSPs and VHDL for FPGAs to optimize real-time algorithms.
We couldn't check your fit for this role — add a CV to your profile to see it next time.
