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Overview of Role As a Advanced Physical Design and Verification Engineer, you will be responsible for the Design Rule Check, Layout vs. Schematic checking and fix all PDV/EMIR/Noise/SigEM violations and errors. You may…
Overview of Role As a Senior Physical Design and Verification Engineer , you will focus on high-performance block-level design, verification, and physical sign-off. You will own the resolution of complex DRC, LVS, ERC,…
Overview of Role We are seeking a highly motivated mmW/RF/Analog Circuit Design Engineer to join TSMC’s RF design team and pioneer the use of advanced technology nodes in RF and mmWave circuit design. This role is…
Overview of Role As a Sr. Physical Design Engineer, you will be responsible for the entire APR implementation flow from RTL-to-GDS that includes synthesis, floorplan, place and route, CTS, STA, and signoff. You will be…
Job Description: -Chip/Block level floorplan, -Clock tree synthesis, -Place & Route, -RC extraction, -STA, timing closure, -IR/EM analysis and fix, -DRC/LVS/ERC analysis and fix, -Tape-out sign off. -APR Flow…
Job Description • Verify TSMC’s product like ARM processor based SOC and memory subsystem test chips • Develop verification methodology and implement test bench components using System Verilog, UVM, and low power…
Job Description • Lead innovation and enablement of custom design methodology and solutions to address critical design challenges in leading-edge technologies. • Collaborate with EDA partners to deliver innovative and…
Einleitung Verstärke unseren Bereich Hardware Entwicklung in Berlin (Deutschland) zum nächstmöglichen Zeitpunkt. Aufgaben Hardware-Entwicklung: Unterstützung bei der Entwicklung und Integration von innovativen…
REQ ID: 131820 JOB TITLE: EDP - Senior Developer LOCATION: Budapest Reimagine the future of modern luxury at JLR Hungary. Here you'll find roles from technical to supply chain. You'll collaborate with global…
Senior digital IC design engineer at ams OSRAM's Plano, TX site who designs, verifies, synthesizes, and brings up silicon for sensor/imaging mixed-signal semiconductors. Core stack: Verilog/SystemVerilog, UVM, low-power and CDC/LEC flows, and Cadence tools like Xcelium, Genus, SpyGlass, and JasperGold.
Winbond Electronics is hiring a CAD AI Engineer at its Zhubei (Hsinchu County) office in Taiwan to build internal AI tooling for engineering teams: RAG systems over documents, Jira and logs, LLM integration (e.g. Gemma, LLaMA), data processing pipelines, and APIs wired into EDA/flow tools. Full-time, onsite, no management or shift duties.
Onsite principal engineer role in Frederick, MD at Leonardo DRS, a defense/intelligence systems maker. Day to day the engineer leads FPGA design end to end — simulation, synthesis, place and route, timing closure, verification — plus digital hardware analysis, prototyping, mentoring junior engineers, and supporting proposals for military electronic warfare and air combat training systems.
Senior Design Verification Engineer on Capgemini Engineering's expanding Ukraine VLSI team: owns IP/SoC verification from RTL through emulation, defines and improves DV methodology, and builds UVM-based testbenches. Core stack is SystemVerilog, UVM/OVM, protocol knowledge (AHB/AXI, PCIe, USB, DDR) and Perl/TCL/Python scripting.
Capgemini Engineering is expanding its Ukraine VLSI team with a Senior Physical Design Engineer in Kyiv who owns full-chip or block-level physical design on advanced 10nm-and-below nodes — floorplanning, place-and-route, clock tree synthesis, timing closure and sign-off — using Synopsys and Cadence EDA tools with Perl/TCL/Python scripting.
Intermediate software engineer at defense company Leonardo DRS in Ottawa/Kanata, ON (hybrid, not remote) building the SHINCOM naval shipboard communication systems. Day to day: analysis, design, and implementation of software subsystems plus reliability work such as FMEA and FRACAS, using C/C++, Ada, Java, or Tcl/Tk.
Design, develop, and field embedded systems for national-security space applications in MIT Lincoln Laboratory's Electronics for Contested Space Group — FPGA firmware (VHDL/Verilog), digital interfaces like SPI/PCIe, DSP, and hardware/software integration, with lab and field testing. Requires an EE/CE graduate degree plus 8 years (or BS + 10) and U.S. citizenship; Top Secret clearance desired.
MIT Lincoln Laboratory's Electronics for Contested Space Group in Lexington, MA is hiring an embedded systems engineer to design, develop, test, and field embedded hardware and FPGA firmware supporting national security space systems. Day-to-day work centers on HDL development (VHDL/Verilog/SystemVerilog), FPGA implementation and debug, hardware/software integration, and lab testing with equipment
A junior design verification and FPGA prototyping role at Capgemini Engineering in Kyiv: modeling image/audio processing algorithms in Python, implementing RTL in SystemVerilog, building FPGA debug environments on a Zybo Z7 board, and developing SV-based and UVM verification environments.
Job Overview Supervises team and oversees quality activities at the site level, ensuring compliance with quality standards, practices, and supports TCL roles in technical quality initiatives. Job Requirements 主要职责 1.…
An analog/mixed-signal design internship at Skyworks Solutions in Nashua, NH, developing timing ICs for clock generation and frequency control. The intern designs transistor-level analog blocks, builds behavioral and noise models, simulates sub-systems, supervises layout, and supports silicon validation, tape-out, and lab measurements.