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The Senior Physical Design Engineer will execute the physical implementation of complex mixed-signal SoCs, from floorplanning through GDSII signoff. The role utilizes Cadence design tools to manage timing, power, and area targets across various process nodes.
Firmware and Diagnostics Engineer at Cadence in Belo Horizonte, Brazil, developing and supporting firmware and diagnostic software for complex hardware systems, particularly working with the Palladium emulation platform.
This posting is for an existing vacancy Description Microchip’s Data Center Solutions Business Unit (DCS) delivers industry leading performance, reliability, and security in Storage Controllers, Memory Controllers,…
Senior engineer who designs and runs system-level tests for next-gen AI chips, debugging failures and optimizing manufacturing readiness.
Drive full-chip physical verification signoff (DRC, LVS, ERC, PERC) for advanced-node SoCs using tools like Calibre, ICV, and Pegasus, collaborating across RTL, PD, CAD, and packaging teams at an AI chip company.
Leads a team in Hyderabad to design and implement high-speed connectivity ASICs for AI infrastructure, using advanced EDA tools and flows for full-chip physical design and tapeout.
This role involves evaluating third-party analog and mixed-signal IP designs to ensure they meet AMD specifications and manufacturing standards. The engineer will use EDA tools and develop automation scripts to analyze circuit performance and resolve design issues before silicon manufacturing.
This role involves evaluating third-party analog and mixed-signal IP designs for AMD processors, ensuring they meet specifications through pre-silicon verification and CAD automation. The engineer will develop scripts and leverage AI tools to improve design analysis workflows and resolve hardware issues before manufacturing.
NextSilicon is reimagining high-performance computing (HPC & AI). Our accelerated compute solutions leverage intelligent adaptive algorithms to vastly accelerate supercomputers, driving them forward into a new…
Senior Staff SOC DFX RTL Design Engineer at AMD's Radeon Technologies Group responsible for planning and implementing DFX features (JTAG, Scan, Boundary Scan, Debug) for next-generation microprocessors, collaborating with architecture, IP design, and physical design teams.
Leads a team designing high-performance, low-power System-on-Chip (SOC) components using Verilog/System Verilog, UPF, and industry-standard EDA tools.
RTL/SOC integration design engineer at AMD Hyderabad, responsible for ASIC design in sub-20nm nodes using Verilog/SystemVerilog, timing analysis, low-power design, and SOC verification tools.
Hands-on test engineer performing functional, performance, and reliability testing on optical transceiver products (SFP, QSFP, etc.) in a manufacturing setting, operating test equipment like BERTs, oscilloscopes, and optical power meters, with some scripting in Python or LabVIEW.
Designs and optimizes integrated circuit layouts from RTL to GDSII using advanced EDA tools, focusing on floorplanning, placement, clock tree synthesis, routing, and physical verification for SoC projects.
This role manages the analog/mixed-signal design environment and CAD infrastructure, overseeing EDA tool ecosystems, compute grids, and design data governance. The manager leads a team to ensure high productivity and reproducibility across silicon programs using tools like Virtuoso, HSPICE, and various version control systems.
Role Purpose The Physical IP Division in Arm Noida creates Memory IPs which are extensively used by thousands of SoC designers around the world to design leading edge chips. We are currently developing memory fast…
As a Design Administrator, you enable and support engineering infrastructure, EDA environments, and automation frameworks for Intel's technology development. Core technologies include EDA tools (Cadence Virtuoso, Calibre, IC Validator), DevOps, CI/CD, and scripting (Python, Shell, TCL, Perl).
Working student supporting embedded software development at Siemens in Erlangen, performing C++ code refactoring, optimizing CMake build environments, fixing lint errors, and maintaining TCL libraries.
Nokia of America Corporation , Sr ASIC Physical Design Engineer (Multiple Positions), Sunnyvale, CA. Support specification, design, and implementation of digital hardware, applying design targets related to cost,…
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