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In a fast-paced, leading-edge environment with endless possibilities of innovating and learning, you will be responsible for leading and defining timing signoff design methodologies of complex and world class…
Company Overview Black Sesame Technologies is a leading automotive-grade computing SoC and intelligent vehicle solution provider. Founded in 2016 and listed on the Hong Kong Stock Exchange, we innovate SoCs for…
The Aerospace Corporation is the trusted partner to the nation’s space programs, solving the hardest problems and providing unmatched technical expertise. As the operator of a federally funded research and development…
We Are At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, enabling everything from self-driving cars to AI-powered systems. We…
Application close date: Applications will be accepted on an ongoing basis until the requisition is closed. At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re…
ASIC Design Engineers — Design-for-Test (DFT) & Physical Design (Synthesis and Timing) – (Experienced, Lead, or Senior) Company: The Boeing Company Boeing Defense, Space and Security is hiring ASIC Design Engineers…
Join Nokia's advanced photonics and semiconductor design team, developing next-generation analog ICs for high-speed optical communication systems. In this role, you will design and lead development of high speed…
Lead a team designing ASICs and FPGAs for SpaceX’s Starshield satellite systems, overseeing RTL implementation, verification, and silicon bring-up to deliver high-speed data processing for national security missions.
Designs and verifies next-generation FPGAs and ASICs for SpaceX’s Starshield national security programs, using Verilog/SystemVerilog and collaborating with verification and physical implementation teams.
Designs and verifies next-generation FPGAs and ASICs for SpaceX’s Starshield national security programs, using Verilog/SystemVerilog, EDA tools, and collaborating with verification and physical implementation teams.
Designs and optimizes advanced ASIC/SOC chips for SpaceX's Starlink satellites and ground systems, focusing on physical implementation, timing closure, and verification using EDA tools.
Designs and implements advanced ASIC/SOC chips for SpaceX’s Starlink network, focusing on physical design flows, timing closure, and signoff checks to enable global satellite internet connectivity.
Designs, scales, and automates high-performance computing infrastructure for SpaceX's Starlink silicon engineering, enabling faster chip design iterations and simulations.
Designs and verifies next-generation ASICs for SpaceX’s Starlink network, using SystemVerilog, UVM, and Python to ensure reliable satellite and ground infrastructure connectivity.
Design Verification Engineer at SpaceX developing and testing next-generation ASICs for Starlink's satellite and ground infrastructure using SystemVerilog, UVM, and Python.
Designs and integrates RF and analog integrated circuits for space-grade hardware, focusing on layout, parasitic minimization, and tape-out for national security projects.
Designs and verifies next-generation ASICs for SpaceX’s Starlink network, ensuring satellite and ground infrastructure connectivity through pre- and post-silicon validation.
Designs and verifies next-generation ASICs for SpaceX’s Starlink network, ensuring chips meet performance and reliability needs for global satellite and ground infrastructure.
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