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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position Overview As a Senior Principal Design Engineer, you will be responsible for the design,…
Physical design intern working on next-generation high-performance processor ASIC physical design and methodology using cutting-edge CMOS process technology for server, 5G/6G, automotive, and networking applications.
Design Intern at Microchip's Data Center Solutions unit writing RTL (Verilog/SystemVerilog) for storage controller SOCs and developing AI-based tools and automated design flows to enhance productivity.
The GPU Digital Frontend Design Engineer will define microarchitecture, design RTL for high-performance GPU/AI accelerator chips, and optimize for power, performance, and area. The role involves collaborating with verification, software, and physical design teams using Verilog/SystemVerilog and standard EDA tools.
The SoC Digital Design Engineer will design and implement hardware accelerators for video codecs and SoC subsystems using Verilog/SystemVerilog. The role involves architecture definition, RTL implementation, and cross-functional collaboration to optimize power, performance, and area for large-scale video platforms.
The Principal Engineer will develop and optimize Resolution Enhancement Techniques (RET) and Optical Proximity Correction (OPC) solutions to improve wafer patterning for advanced memory technologies. The role involves leading mask development projects, collaborating across R&D and manufacturing, and mentoring engineers in lithography optimization.
Systems Engineer, Senior Company: The Boeing Company The Boeing Defense, Space & Security , Space Mission Systems (SMS) organization has an exciting opportunity supporting Proprietary programs and is seeking a…
The Senior Backend Design Automation Engineer will develop and maintain backend design flows for new semiconductor process nodes, integrating PDKs and EDA tools to support FPGA design teams. The role involves modernizing design infrastructure and applying automation and AI/ML techniques to optimize flow development and regression testing.
Job Details: Job Description: Altera is seeking a technically strong Transceivers & Protocol IP Application Engineer to be based in San Jose California Altera Office to help customers and partners successfully…
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Profile Role Title Lead Design Engineer, SoC / Subsystem / IP Design Experience 4to 18 years…
Design Verification Engineer responsible for developing verification plans, test benches, and running regressions to ensure first-pass silicon success for analog and mixed-signal ICs at Texas Instruments in Dallas.
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Designs and implements test solutions for advanced AI/photonics-based chips, working across digital, analog, and photonic logic to ensure manufacturability and bring products to market.
Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant leaps in human progress. The company invented the world’s first 3D-stacked photonics engine, Passage™, capable of…
Designs and automates photonics Process Design Kits (PDKs) using Python and EDA tools, ensuring accurate simulation and layout verification for high-speed AI data center hardware.
As a Silicon Validation/Emulation Design Engineer, you will work in a team developing Wireless SoCs with custom hardware accelerators, as well as multiple ARM-based sub-systems. You will be a key contributor in our…
Junior engineer builds and runs test environments to verify next-gen AI connectivity chips using SystemVerilog/UVM and debugs hardware issues with design teams.
Leads a team of engineers to design advanced semiconductor packages (FCBGA/FCCSP, chiplet-based) for AI connectivity solutions, collaborating with OSATs and cross-functional teams using Cadence Allegro APD/SiP.
Manages a team of physical design engineers in Toronto to implement high-speed connectivity ASICs for AI infrastructure, using advanced EDA tools and TSMC nodes.
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