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Design and develop DSP blocks for quantum computing systems using ASIC flows, RTL, and EDA tools while collaborating with cross-functional teams.
Design a radiation-tolerant RISC-V microcontroller ASIC for CERN’s particle physics detectors using 65/28 nm CMOS, RTL-to-tapeout with fault-tolerant techniques and post-silicon validation.
Principal firmware engineer leading FPGA development for aerospace navigation systems, defining standards and mentoring teams to ensure DO-254 compliance and high-reliability designs.
Design and verify PCIe interconnect IP for AMD’s GPUs, APUs, servers, and consoles using UVM/SystemVerilog, collaborating with global teams.
Designs and implements ASICs for quantum computing systems, focusing on DSP blocks and RTL development while collaborating with cross-functional teams.
Drive the product roadmap and GTM for Broadcom’s PCIe switch line, aligning AI/ML server architectures with market needs and collaborating with hyperscalers and OEMs.
Design and verify FPGA hardware using VHDL for radar, RF/EO DSP, and embedded systems; collaborate with systems engineers and verify designs with constrained-random tests.
We are looking for an experienced Senior Operations Analyst to support two key engineering organizations within Arm's Solutions Engineering Group: a team developing Technology IPs and a Central Engineering team…
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description The ideal candidate will be energetic, innovative and enthused with how to help customers,…
Senior FPGA engineer building hardware prototypes and validating next-gen satellite communications ASICs, from FPGA bring-up to first-silicon debug.
At Atom Computing, we build quantum computers using arrays of optically trapped neutral atoms that will empower customers to achieve unprecedented computational breakthroughs. Join a world-class team of scientists,…
Build and debug SystemVerilog/UVM testbenches for ASIC IP blocks powering 5G networks, from block-level to top-level verification and SW-driven validation.
Designs and optimizes custom silicon for Google Cloud, focusing on performance, power, and area while collaborating with cross-functional hardware teams.
Design and optimize FPGA-based hardware for ultra-low-latency trading infrastructure, integrating Ethernet stacks and custom logic to parse and route exchange data efficiently.
Leads cross-functional teams to develop automotive-grade ASICs, ensuring compliance with ISO 26262 and AEC-Q100 while managing schedules, budgets, and quality targets.
Design analog and mixed-signal high-voltage ICs for automotive systems like sensor interfaces and smart power devices, owning transistor-level circuits and guiding chip integration.
Physical design engineer implementing advanced ASICs from netlist to GDSII using PnR tools, focusing on timing closure, PPA optimization, and tape-out signoff.
Designs and automates ASIC front-end methodologies for IP/SoC projects, using EDA tools like SpyGlass and scripting in Python/Perl/TCL to improve design checks and integration flows.
Designs and runs SystemVerilog/UVM testbenches to verify FPGA IP blocks and SoC designs, using coverage-driven methods and assertions to ensure first-pass silicon success.
Designs and optimizes semiconductor SoC timing, power domains, and verification for ASIC releases using synthesis and static timing analysis tools.
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